Overranged Converter Recovers Quickly


How do you verify overrange recovery in high-sample-rate converters?

RAQ:  Issue 106


Application Note AN-835, Understanding High-Speed ADC Testing and Evaluation, defines overrange recovery as the time required for an ADC to recover to the rated accuracy after an input transient moves from 10% above positive full scale to 10% above negative full scale or from 10% below negative full scale to 10% below positive full scale.

In the early days of high-speed ADCs, overrange recovery was tested with a full-scale pulse that was offset either 10% positive or 10% negative. The ADC was tested to see how many samples were required for it to recover from the overrange. With typical ADC input ranges of several volts, recovery required several clock cycles. The latest generation of GSPS ADCs specifies a recovery time of one or two clock cycles, so creating a pulse to measure the recovery time is nearly impossible. How, then, can we verify it?

While evaluating one of our latest 12-bit, 2.5-GSPS ADCs, we came up with an interesting way to stress the ADC to prove the recovery. The concept is illustrated in Figure 1a. The ADC is sampling at its full rate, 2.5 GSPS, with a 5.000526210 GHz analog input that is clipping the converter’s input range. This will result in the converter’s digital output representing the alias frequency from the 5th Nyquist zone at 526.210 kHz. Figure 1b zooms in on the samples as the aliased signal comes back in range. It also superimposes the actual analog input, showing how the analog input swings from out of range on the positive side to out of range on the negative side to barely back in range on the positive side in the time between the last clipped sample and the first sample that is back in range. Keep in mind that the inherent thermal noise of the ADC has to be taken into account, so the converter’s noise could bring a signal that was just out of range back in range by a few codes. That’s exactly what we saw in the lab, so I feel good about this ADC’s overrange recovery under a very stressful condition.

RAQ:  Issue 106 Figure 1
Figure 1. ADC overrange recovery.


David Buchanan

David Buchanan

David Buchanan received a BSEE from the University of Virginia in 1987. Employed in marketing and applications engineering roles by Analog Devices, Adaptec, and STMicroelectronics, he has experience with a variety of high-performance analog semiconductor products. He is currently a senior applications engineer with ADI’s High Speed Converters product line in Greensboro, North Carolina.