Setting down your third cup of coffee, you pick up a pile of specifications with a sigh. Today you face a familiar challenge: Develop a next-generation platform that meets cutting-edge requirements on an implausible timeline while remaining within an unjustly slim budget, and do it all with a smile. You must choose the right vendors for the project, and to meet these ever more strenuous goals, you need vendors that provide quality support alongside their core products.
Analog Devices rises to meet these expectations with such support software as the Analog Filter Wizard and ADC modeling tools. Now Analog Devices is taking the next step with a comprehensive online product evaluation tool called Virtual Eval. Virtual Eval employs detailed software models to simulate crucial part performance characteristics without the purchase of hardware. The overworked engineer can configure a variety of operating conditions and device features to establish custom use cases. The configuration settings are dispatched to Analog Devices servers to kick off a simulation job. Within seconds, the completed simulation results display as graphs and performance metrics in the browser window.
Virtual Eval can solve a wide variety of design problems to accelerate the product development cycle. The remainder of this article covers two such problems out of many. In the first, a data acquisition scenario, you must balance throughput rate and noise performance to choose the right precision converter. In the second, while working on a radio receiver, you need to digitize some spectra with a minimum dynamic range requirement, while keeping overall system power low. In both cases, Virtual Eval facilitates faster design decisions with greater confidence through the use of online simulation.
Wading through the specification tome, the key requirements slowly start to emerge:
- 4-channel signal acquisition, ±75 mV
- 18-bit performance or higher
- 50 Hz rejection below –40 dB
- Settling time of 50 ms, but faster is better
Spoiler alert! The Analog Devices AD7193 is the right part for this job. The traditional method for making the correct part selection is by utilizing the specifications in the product's data sheet to analyze the component's performance under various filtering and application conditions. There is a lot of manual labor involved in this method and data sheets cannot provide performance specifications for every possible combination of frequency selection and use case conditions of interest to a wide variety of customers. What you really need is an interactive tool like Virtual Eval to understand product performance through custom simulations tailored to your particular use case.
The first screen you see is the product chooser.
Under Precision ADC, find the AD7193. One click loads the evaluation session.
The Functional Block Diagram view illustrates the layout of the AD7193. Clickable components of the diagram reveal the associated configurable settings in the accordion on the left-hand side of the screen. Select the reference voltages and observe a VREF of 2.5 V. Then, select the PGA component, and change the PGA gain from 128 to 32, allowing for an analog input range of ±2.5 V/32 = ±78.125 mV. This satisfies the amplitude specification. Finally, click the Run button at the top of the Settings column. Remote servers run a collection of simulations, and deliver the performance results back to the Virtual Eval client.
To interpret the results, switch to the Waveform view using the tabs near the top of the screen.
The Results column contains dependent variables computed in the simulation, such as noise and power characteristics. The peak-to-peak resolution is 18.531 bits, which satisfies the specifications; however, the settling time of 80.103 ms does not.
In precision converters, this settling time is a function of the filter configuration. Switching to the H(f) Response view gives insight into the filtering performance of the product.
The specifications require –40 dB of rejection at 50 Hz, but the actual rejection power is –131 dB! That surplus of rejection can be sacrificed to improve settling time. To dial back the filtering, select the ADC element in the Settings column, and change FS from 96 to 48. To ensure there is still a zero in the filter response at 50 Hz, increase the Averaging from 1 to 2. Lastly, change the sinc order from 4 to 3 to save a little more settling time. Then run the simulation again.
The rejection at 50 Hz is now about –41 dB, which satisfies the specification. There is no way to determine this from the data sheet, since Analog Devices does not publish the formulas used to compute frequency rejection. Only an interactive simulation allows the engineer to directly verify product performance in particular scenarios such as this.
Switching back to the Waveform view reveals that the settling time is just 40.103 ms due to the reduction in filtering, easily meeting the specifications.
Your company's new platform must digitize approximately 50 MHz worth of spectrum located at 354 MHz with 72 dB of signal-to-noise ratio. Fast forward to a design choice to use an RF ADC, the AD9680. It has a sampling rate of 1 GSPS, an on-chip digital downconverter, and a flexible JESD204B serial interface. Its data sheet is very detailed and thorough, but as mentioned previously, it just cannot possibly address every potential use case. Virtual Eval can, so you open it from the AD9680 product page.
Select the High Speed ADC category and click on the AD9680.
You are presented with the default Virtual Eval session starting with the Functional Block Diagram view:
Visible are DDCs and JESD204B, both a good sign based on the requirements. Set the Single Tone input Frequency to 354 MHz to represent the use case and press Run.
Virtual Eval performs a simulation and a full spectral analysis. The figure of merit in this case is the SNR. 63.9 dB is certainly insufficient, but that can be remedied. Switch the DDC from Disabled to Enabled. This presents several new options for digital signal processing to improve performance.
Set the NCO Frequency to 354 MHz so that the spectrum is centered appropriately. Additionally, switch the C2R (complex-to-real) to Enabled. Switching to real values halves the amount of data transmitted, reducing I/O power between the ADC and FPGA. Press Run again to see the new simulation results.
The input tone is centered as expected. However, there is a large Fundamental Image near the right side of the graph. Fortunately, the specification requires just 50 MHz of bandwidth, much less than the 500 MHz currently digitized. The solution here is to reduce the spectrum under consideration, simultaneously improving SNR and filtering out the image. In the Settings column, change the DDC decimation from 1 to 8, and Run again. This reduces the spectrum to 500 MHz/ 8 = 62.5 MHz.
The fundamental image is digitally filtered out, and the SNR is better than 72 dB. Since the converter is only digitizing 62.5 MHz of spectrum, the data link between the ADC and FPGA is nearly optimal.
Virtual Eval provides a fast, convenient, low risk way to virtually interact with products through online simulation. It illustrates complex product features, and allows engineers to discern whether a product can satisfy their requirements under custom operating conditions. No other form of product evaluation experience enables the same level of detail and interactivity through the convenience of the Web browser.
This walkthrough demonstrates only a small slice of the features available on Virtual Eval. More features and more products are often added to the Beta site. Please take this opportunity to be a part of the on-going development process by trying Virtual Eval yourself. We welcome any and all feedback via the Feedback tab in the lower right. As Virtual Eval continues to develop and grow, we hope to bring online simulation to the center stage of the product evaluation and design process.