Introduction
In traditional transceiver designs, 50Ω singleended interfaces are widely used in RF and IF circuits. When circuits are interconnected, they should all see matching 50Ω output and input impedances. In modern transceiver designs, however, differential interfaces are frequently used to obtain better performance in IF circuits, but implementing them requires designers to confront several common issues, including impedance matching, commonmode voltage matching, and difficult gain calculations. An understanding of differential circuits in transmitters and receivers is helpful for optimizing gain matching and system performance.
Differential Interface Advantage
Differential interfacing has three main advantages. First, differential interfacing can suppress external interference and ground noise. Second, evenorder output distortion components can be suppressed. This is very important with zerointermediatefrequency (ZIF) receivers because evenorder components appearing in the lowfrequency signal cannot be filtered out. Third, the output voltage can be twice that of singleended output, thus improving output linearity by 6 dB on a given power supply.
This article discusses interfacing solutions for three cases: a ZIF receiver, a superheterodyne receiver, and a transmitter. These three architectures are widely used in wireless remote radio units (RRU), digital repeaters, and other wireless instruments.
ZIF Receiver Interface Design and Gain Calculation
In zeroIF (ZIF) receiver designs, the IF signal is complex, with dc and very low frequency signals providing useful information. Typical demodulators may provide optimum performance when driving 200Ω to 450Ω loads, and ADC drivers generally have input impedance other than 50Ω, so interfacing systems with dccoupled circuits is both critical and difficult.
Figure 1 shows a ZIF receiver configuration using two ADL5523 lownoise amplifiers (LNAs), an ADL5380 400MHz to 6000MHz quadrature I/Q demodulator, an ADF4350 wideband synthesizer as a local oscillator (LO), and an AD8366 twochannel digitally programmable variablegain amplifier (VGA). Table 1 shows the relevant ADL5380 interface and gain parameters.
Table 1. ADL5380 Interface and Gain ParametersTest Condition 
V_{S} = 5 V, T_{A} = 25°C, f_{LO} = 900 MHz, f_{IF} = 4.5 MHz, P_{LO} = 0 dBm, Z_{IN} = 50 Ω 

Parameters 
Values 
Comments 
VoltageConversion Gain 
6.9 dB 
450Ω differential load on I and Q outputs 
5.9 dB 
200Ω differential load on I and Q outputs 

CommonMode Output Voltage 
2.5 V 
ADJ connected to V_{S} 
I/Q Differential Output Impedance 
50 Ω 
When interfaced with the AD8366, which has a 217Ω differential input impedance, the ADL5380 has 5.9dB voltage gain and –0.5dB power gain [5.9 dB – 10log (217/50)]. For best performance, the commonmode voltage between the ADL5380 and AD8366 is set to 2.5 V by connecting the ADL5380 ADJ pin to V_{S}. A differential fourthorder Butterworth lowpass filter with 0.5dB insertion loss, placed between the ADL5380 and the AD8366, suppresses noise and unwanted highfrequency components. While the filter will cause some mismatch, it will be tolerable at baseband frequencies.
Table 2. AD8366 Interface and Gain ParametersTest Condition 
V_{S} = 5 V, T_{A} = 25°C, Z_{S} = 200 Ω, Z_{L} = 200 Ω, f = 10 MHz 

Parameters 
Values 
Comments 
VoltageConversion Gain 
4.5 dB 
Minimum digital gain setting 
20.25 dB 
Maximum digital gain setting 

CommonMode Output Voltage 
1.5 V 
Minimum 
2.5 V 
Maximum or input selfbias 

Differential Input Impedance 
217 Ω 

CommonMode Ouput Voltage 
1.6 V 
Minimum 
3 V 
Maximum 

2.5 V  VCMA and VCMB left floating  
Differential Output Impedance 
28 Ω 

Linear Output Swing 
6 V pp 
1dB gain compression 
The commonmode output voltage of the AD8366 can be set to 2.5 V; it has best linearity when VCM is left floating. Unfortunately, the AD6642 has best performance with 0.9V commonmode input voltage (0.5 × AVDD). Because the commonmode output voltage of the AD8366 must be between 1.6 V and 3 V, the AD6642 VCM and AD8366 VCM terminals cannot be connected directly, and resistors must be used to divide the AD8366 commonmode output voltage down to 0.9 V.
For best performance, the AD8366 should drive a 200Ω load. To achieve the desired commonmode level and impedance match, 63Ω series resistors and 39Ω shunt resistors are added after the AD8366. This resistor network will attenuate power gain by 4 dB.
The AD8366 output can swing 6 V pp, but the 4dB attenuation provided by the resistor network limits the voltage seen by the AD6642 to 2.3 V pp, protecting it from damage caused by big interference spikes or uncontrolled gains.
A differential sixthorder Butterworth lowpass filter with 1.5dB insertion loss, placed between the AD8366 and the AD6642, filters unwanted highfrequency components. The complete differential interface for the I channel is shown in Figure 2.
To preserve enough margin to account for gain variation over temperature, the AD8366 gain is set to 16 dB for the normal mode.
In this configuration, the gain of the whole signal chain is
5.9 dB – 10log (217/50) – 0.5 dB + 16 dB – 10log (200/217) – 1.5 dB – 4 dB
= 9.9 dB.
The two LNAs inserted in cascade ahead of the ADL5380 achieve 32 dB of gain. With the analogtodigital converter configured for a 2V pp swing and 78Ω equivalent input impedance, it is able to handle a –34dBm singletone RF input signal. If the input signal has a 10dB peaktoaverage ratio (PAR) when modulated, a –41dBm input signal is the maximum signal that the receiver can handle without changing the VGA setting.
In the other words, voltage gain can be used to calculate the signal chain link budget. When the input port impedance is equal to that of the output port, the voltage gain is equal to power gain. The voltage gain of the whole signal chain is
32 dB + 5.9 dB – 0.5 dB + 16 dB – 1.5 dB – 8 dB = 43.9 dB.
For singletone signal input, to get a 2V pp swing range, the proper input power is
8 dBm – 43.9 dB + 10log (78/50) = –34 dBm.
The result is a close match to the calculated power gain.
In some applications, the ADL5380 may need to be connected directly to the AD6642, in which case a 500Ω resistor can be added to the AD6642 differential inputs to improve matching. The ADL5380 voltage gain will be 6.9 dB, with the same commonmode problem as with the AD8366. A 160Ω series resistor and 100Ω shunt should be used to achieve a 500Ω load and the desired commonmode voltage. Again, the resistor network attenuates the voltage by 8 dB (and the power by 4 dB).
A lowpass filter with 1.5dB insertion loss, placed between the ADL5380 and AD6642, filters unwanted frequency components. The input impedance is 50 Ω, and the output impedance is 500 Ω. In this configuration, the gain of the whole signal chain is
6.9 dB – 10log (500/50) – 1.5 dB – 4 dB = –8.6 dB.
Superheterodyne Receiver Interface Design and Gain Calculation
In superheterodyne receivers, the system uses ac coupling, so the dc commonmode voltage does not have to be considered when interfacing these circuits.
Many mixers, such as the ADL535x and ADL580x, have 200Ω differential output impedance, so the power gain and voltage gain are presented separately for different output impedances.
Figure 3 shows one channel of a superheterodyne receiver implemented with an ADL5523 lownoise amplifier; an ADL5356 dual balanced mixer with LO buffer, IF amplifier, and RF balun; a lowpass filter; an AD8376 dual ultralow distortion IF VGA; another lowpass filter; and an AD6642 dual IF receiver.
This design uses a 140MHz IF and 20MHz bandwidth, so the parts can be accoupled.
The AD5356 has best performance with a 200Ω load, but the AD8376 has 150Ω input impedance. Thus, to suppress mixer output spurs and provide better impedance matching, the differential LC filter must have 200Ω input impedance and 150Ω output impedance. In applications where the output band signal must be suppressed by a sharp filter, a differential SAW filter can be used, but this introduces loss and group delay in the receiver signal chain. A differential fourthorder bandpass Butterworth filter may be suitable for many wireless receivers because the RF filter can provide enough attenuation for outofband interference.
Table 3. ADL5356 and AD8376 Interface and Gain ParametersADL5356 Test Condition 
V_{S} = 5 V, T_{A} = 25°C, f_{RF} = 1900 MHz, f_{LO} = 1760 MHz, LO power = 0 dBm 

Parameters 
Values 
Comments 
VoltageConversion Gain 
14.5 dB 
Z_{SOURCE} = 50 Ω, differential Z_{LOAD} = 200 Ω differential 
CommonMode Output Voltage 
2.5 V 
ADJ connected to V_{S} 
Power Conversion Gain 
8.2 dB 
Including 4:1 IF port transformer and PCB loss 
AD8376 Test Condition 
V_{S} = 5 V, T_{A} = 25°C, R_{S} = R_{L} = 150 Ω at 140 MHz 

Parameters 
Values 
Comments 
Differential Input Resistance 
150 Ω 

Voltage Conversion Gain 
–4 dB 
Minimum digital setting 
20 dB  Maximum digital setting 

Output Impedance 
16 kΩ  0.8 pF 
The AD8376’s currentoutput circuit has high output impedance, so 150Ω is needed between its differential outputs. Another differential filter must attenuate the second and thirdharmonic distortion components, so this 150Ω load is divided into two parts. First, a 300Ω resistor is installed in the output of the AD8376. Another 300Ω resistor is formed by two 165Ω resistors and the ADC’s 3kΩ input impedance. The two 165Ω resistors also provide the dc commonmode voltage for the ADC input. The LC filter’s input and output impedances are both 300 Ω. Perfect source and load matching is very important for highIF applications. The complete interface is shown in Figure 4.
In the receiver, a 20dB LNA is installed ahead of the mixer. The filter after the mixer has 2dB insertion loss; the filter between the AD8376 and the ADC has 1.2dB insertion loss. The AD8376 gain is set to 14 dB to provide enough margin to account for temperature variation. The overall gain of the receiver is
20 dB + 8.2 dB – 2 dB + 14 dB – 1.2 dB = 39 dB.
To limit the ADC input voltage to less than 2 V pp, the power transmitted to the 150Ω resistance (300 Ω  (165 Ω × 2)  3 k Ω) should be smaller than 5.2 dBm. The maximum input power for the receiver is thus –33.8 dBm for a singletone signal. If the input signal is a 10dB PAR modulation signal, the maximum input signal using this gain setting is –40.8 dBm.
Transmitter Interface Design and Gain Calculation
For Txchannel designs, both ZIF and superheterodyne architectures have similar interface characteristics, and both need dc coupling between the TxDAC^{®} and the modulator. Most modulators’ IF input circuits should be biased by a dc voltage externally; the TxDAC output can provide dc bias for the modulator in a dccoupled mode. Most highspeed DACs have current outputs, so an output resistor is needed to produce an output voltage for the modulator.
Figure 5 shows a superheterodyne or ZIF transmitter implemented with an AD9122 TxDAC, a lowpass filter, an ADL537x quadrature modulator, another RF filter, an ADF4350 synthesizer, an ADL5243 digitally controlled VGA, a power amplifier, and an AD562x DAC to control the power amplifier’s (PA) gate voltage.
For the AD9122, the fullscale output current can be set between 8.66 mA and 31.66 mA. For fullscale currents greater than 20 mA, the spuriousfree dynamic range (SFDR) is decreased, but the output power and ACPR of the DAC decrease with lower fullscale current settings. A suitable compromise is a 0mA to 20mA current output consisting of a 20mA ac current riding on a 10mA dc level.
Table 4. AD9122 and ADL5372 Interface and Gain ParametersAD9122 Test Condition 
AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V 

Parameters 
Values 
Comments 
FullScale Output Current 
8.66 mA 
Minimum digital full scale setting 
31.66 mA  Maximum digital full scale setting  
Output Resistance 
10 MΩ 
ADL5372 Test Condition 
V_{S} = 5 V, T_{A} = 25°C, fLO = 1900 MHz, f_{IF} = 140 MHz 

Parameters 
Values 
Comments 
Output Power 
7.1 dBm 
V_{IQ} = 1.4 V pp differential 
I and Q Input Bias Level 
0.5 V 
Recommended 
Differential Input Impedance 
2900 kΩ 
The input circuit of the ADL5372 needs a 0.5V commonmode voltage, which is provided by a 10mA dc current flowing through a 50Ω resistor. The 0mA to 20mA ac current is shared by two 50Ω resistors and a 100Ω resistor. The ac voltage between the modulator inputs is thus 20 mA × ((50 × 2)  100) = 1 V pp. The filter between the TxDAC and the modulator removes unwanted frequency components. The input and output impedance of the filter is 100 Ω. The complete interface is shown in Figure 6.
With a 50Ω output, the voltage conversion gain of the ADL5372 is 0.2 dBm. With a 13dB PAR modulator signal, the average power must be reduced by at least 15 dB for the Tx digital predistortion process. With a 1V pp singletone input to the ADL5372, the average modulator output power is 7.1 dBm – 2.9 dBm = 4.2 dBm. If the 2.2dBm insertion loss of the lowpass filter is considered, the peak output power is 4.2 dBm – 2.2 dBm = 2 dBm. In this state, an average output power of –10 dBm is presented at the output of the modulator.
With an 11dBm average power signal, a PAdriver with 26dBm P1dB is needed in the Tx signal chain. If a 2dB insertionloss RF filter is needed to suppress LO feedthrough and sideband output of the modulator, then the gain block and PA driver have to provide a total of 21dB gain. The ADL5243 VGA with integrated gain block, digitally controlled attenuator, and PA driver is suggested for this application.
Conclusion
This paper describes ZIF and superheterodyne receiver differential interfaces for the demodulator, IF VGA, mixer, and analog port of the ADC, as well as transmitter differential interfaces between the TxDAC and FMOD, using Analog Devices parts for active portions of the signal chain. Gain calculations and simulation results are presented for the application filters that were designed for these circuits. Additional information can be found in the following references.
References
Circuit Note CN0018, Interfacing the ADL5372 I/Q Modulator to the AD9779A DualChannel, 1 GSPS HighSpeed DAC.
Circuit Note CN0134, Broadband Low Error Vector Magnitude (EVM) Direct Conversion Transmitter.
Calvo, Carlos. “The differentialsignal advantage for communications system design.” EE Times.