AN-2589: ADRV904x Clocking Application Note

Scope

This application note assists in designing the ADRV904x device clock input and supplements the information found in the documents mentioned in the Documents Needed section. The local oscillator (LO) phase noise of the ADRV904x can be impacted by the jitter of the clock providing the device lock (DEVCLK) into the IC. The data sheet specification for LO phase noise is measured with an ideal DEVCLK. This application note studies the impact of the AD9528 on the LO phase noise and provides a method to modify the evaluation board to provide an ideal DEVCLK to the IC.

Documents Needed

• ADRV904x system development user guide
• ADRV904x evaluation system user guide
• AD9528 data sheet

Evaluation Board (EVB) Clock Tree

The block diagram for the EVB clock tree is shown in Figure 1. The ADRV904x EVB uses the AD9528 to generate the device clock (DEVCLK) and SYSREF signals to the IC.

The AD9528 not only provides the DEVCLK and SYSREF clocks to the ADRV904x but also to the FPGA board (ADS10). The block labeled ADCLK944 is a buffer device that is not populated on the EVB. There are 0 Ω resistors and do not install (DNI) pads available to allow some modifications to the clock tree during evaluation.

A description of the signal path from input to output of the clock tree on the EVB is as follows. Starting at the top left of the diagram is the physical SMA connection of the reference clock to the EVB (labeled as Ref Clock SMA J901). The Ref Clock signal is passed through a balun to convert the signal from single-ended to differential. The output of the balun is node named DEVCLK_BUFF±. There is a physical connection from this point to the REFA input of the AD9528. The connection is not shown on the diagram because it needs to be routed across the diagram. The AD9528 locks onto the Ref Clock signal and jitter clean the reference clock and frequency upconvert to the final device clock frequency. All clocks generated by the AD9528 are shown on bottom right of diagram. A DEVCLK and SYSREF go to the ADRV904x, while clocks go to the ADS10 board (labeled with prefix the FPGA_). When the AD9528 operates as a jitter cleaner, the reference clock to the EVB can come from a high phase noise (low-cost) device. For functionality and performance specifications, refer to the AD9528 data sheet. It is recommended, but not required, that the reference clock source be phased-locked to any analysis equipment that is used to evaluate the ADRV904x. This is to eliminate any frequency errors between the ICs. An example is a spectrum analyzer used to measure transmitter spectrum.

The most relevant figure of merit of any clock source or LO is its phase noise. Phase noise can be measured on the EVB by connecting to any of the transmitter outputs while transmitting a DC offset. Figure 2 shows how Analysis | Control | Evaluation (ACE) software can be used to generate a DC offset vector to play as a test tone. Here, the I signal is 0, while the Q signal is set to a constant digital-to-analog converter (DAC) full-scale negative value. This causes the LO frequency to be transmitted from the transmitter as a single tone. Beware of the measurement capability of the instrument used to measure phase noise because it can limit the accuracy of the results.

Figure 3 shows a typical phase noise measurement of the LO at 3500 MHz that can be found in the ADRV904x data sheet. This is measured with an ideal DEVCLK to the ADRV904x.

Figure 4 shows a measured phase noise on the ADRV904x EVB. A higher level of noise can be seen at lower frequency offsets. This increased noise is attributed to the AD9528.

If LO phase noise close to data sheet performance is required, then the changes to the EVB shown in Figure 5 are required. R924 and R925 must be moved to the pads for R920 and R921. J902 and J903 are now the differential clock inputs AC-coupled directly to the ADRV904x device clock input. For signal level specification for the ADRV904x device clock input, refer to the ADRV904x data sheet. In this configuration, the Ref Clock SMA J901 still provides the REFA clock to the AD9528, ensuring it generates the required SYSREF and FPGA clocks. Most high-quality signal generates have noise levels adequate for DEVCLK source. For reference clock phase noise requirements, refer to the ADRV904x user guide.

Figure 6 shows the phase noise results using an external reference clock. The results are very close to the ones listed in the data sheet.

Table 1 shows a summary of all three measurement conditions for comparison. The second column lists the data sheet noise, and the fourth column is of the modified EVB with the AD9528 bypassed. The results are as expected, the AD9528 impacts the noise slightly.

Changing the Voltage-controlled Crystal Oscillator (VCXO)

The EVB is equipped with a 122.88 MHz single-ended complementary metal-oxide semiconductor (CMOS) VCXO. The power supply for the VCXO is 3.3 V. The EVB VCXO pad can accommodate multiple dimension VCXO modules and single-ended or differential outputs. Currently, the ADRV904x ACE plugin can only support single-ended CMOS. Refer to the AD9528 data sheet for VCXO input specifications.

The ACE user interface to adjust the clock settings is shown in Figure 7. In the Clock Settings area, click the Device Clock Rate dropdown menu, and select Custom. Enter the required frequencies for the clocks. Next go to the ACE tab ADRV904x, and click Program. The configurator generates a profile with the required DEVCLK frequency and program the IC. If Phase3 of initialization is completed with no errors, then the clock frequencies are accepted.

Conclusions

The ADRV904x data sheet values of phase noise and transmitter EVM across LO frequency are summarized in columns 1 through 4 of Table 2. The integrated noise is specified in °RMS and listed in second column. Multiplying this value by π/180 × 1000 converts the noise to m-radians RMS shown in the third column. Transmitter EVM is specified in % and listed in the fourth column. Comparing columns 3 and 4 shows that EVM is close to value of the integrated phase noise (radians), indicating that EVM is dominated by the integrated phase noise. Therefore, any degradation in phase noise also results in degradation of EVM.

The EVM of each device in the transmitter signal chain can be combined in a root-sum-square (RSS) manner to get total system EVM. The power amplifier typically dominates the EVM of the system. If a user uses an example where the power amplifier signal chain (nonlinearities and crest factor reduction (CFR)) contributes 2% to the EVM budget, the total system EVM can be calculated.

EVM of the transceiver and EVM of the power amplifier are RSS added together to get the total EVM. Equation 1 and Equation 2 show these calculations. There is only a small difference in total EVM from an ideal and the AD9528 as DEVCLK.

Depending on the system budget for EVM, the phase noise with the AD9528 can be adequate and a suitable source for DEVCLK.

The ADRV904x data sheet ideal DEVCLK system EVM budget is calculated as follows: