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ADSP-21061

50 MHz、150 MFLOPS、5v、浮点SHARC

英文数据手册

新设计不推荐使用本产品

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概览

优势和特点
产品详情

优势和特点

50MHz (20ns instruction rate) SISD SHARC Core
150MFLOPs peak performance
Code compatible with all SHARC processors
Supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math

1Mbit of on-chip dual-ported SRAM
Glueless connection for scalable DSP multiprocessing
Two synchronous serial ports with independent transmit and receive functions
6 Channel DMA controller
Host Processor Interface

产品详情

The ADSP-21061 is a member of the powerful SHARC ® family of floating point processors. The SHARC ® Super Harvard Architecture Computerare signal processing microcomputers that offer new capabilities and levels of integration and performance.

The ADSP-21061 is a 32-bit processor optimized for high performance DSP applications. The ADSP-21061 combines the ADSP-21000 DSP core with a dual-ported on-chip SRAM and an I/O processor with a dedicated I/O bus to form a complete system-in-a-chip.

Fabricated in a high-speed, low-power CMOS process, the ADSP-21061 has a 20 ns instruction cycle time operating at 50 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle.

The ADSP-21061 SHARC ® combines a high-performance floating-point DSP core with integrated, on-chip system features, including a 1 Mbit SRAM memory, host processor interface, DMA controller, serial ports and parallel bus connectivity for glueless DSP multiprocessing.

产品分类

音频和视频产品
- SHARC处理器

处理器和DSP
- SHARC处理器

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文档

数据手册 (1)

ADSP-21061/ADSP-21061L: Commercial Grade SHARC Family DSP Microcomputer Data Sheet (Rev. D)

应用笔记 (46)

EE-112: Class Implementation in Analog C++

EE-332: 周期计数与分析

EE-332: Code example (Rev 2, 03/2008)

EE-332: Cycle Counting and Profiling (Rev. 2)

EE-332: Code example

EE-328: 将ADSP-2106x/2116x 的设计移植到ADSP-2126x/2136x/ 2137x SHARC®处理器系统 (Rev. 1)

EE-305: 基于SHARC®处理器的系统设计与调试 (Rev. A)

EE-340: SHARC®处理器和Blackfin®处理器的SPI 连接 (Rev. 1)

EE-340: Code example (Rev 1, 07/2008)

EE-175: 仿真器与EZ-KIT Lite®评估系统问题解决指南 (Rev. 10)

EE-175: RMA forms (Rev 10, 11/2007)

EE-68: JTAG 仿真技术参考 (Rev. 10)

EE-340: Connecting SHARC^® and Blackfin^® Processors over SPI (Rev. 1)

EE-340: Code example

EE-323: Implementing Dynamically Loaded Software Modules (Rev. 1)

EE-323: Associated Code

EE-72: Generation Boot EPROMS for the SHARC's EZ-KIT Lite's (ADSP21061 with an ID=001)

EE-330: Windows Vista Compatibility in VisualDSP++ 5.0 Development Tools (Rev. 1)

EE-328: Migrating from ADSP-2106x/2116x to ADSP-2126x/2136x/2137x SHARC® Processors (Rev. 1)

EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev. 14)

EE-175: Associated Files

EE-280: In-Circuit Flash Programming on ADSP-2106x SHARC® Processors (Rev. 2)

EE-280: Code Example (Rev 2, 03/2007)

EE-56: Tips and Tricks on SHARC® EPROM and Host Boot Loader (Rev. 3)

EE-84: External Port DMA Modes of Operation for SHARC Processors (Rev. 2)

EE-84: Code Example (Rev 2, 2/2007)

EE-253: Power Bypass Decoupling of SHARC® Processors (Rev. 1)

EE-305: Designing and Debugging Systems with SHARC Processors (Rev. 1)

EE-267: Implementing In-Place FFTs on SISD and SIMD SHARC® Processors (Rev. 1)

EE-267 Software Code

EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev. 1)

EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev. 3)

EE-202 Software Code

EE-241: SHARC® DSPs to TigerSHARC® Processors Code Porting Guide (Rev. 1)

EE-241 Software Code

EE-191: Implementing a Glueless UART Using The SHARC® DSP SPORTs

EE-191 Software Code

EE-68: Analog Devices JTAG Emulation Technical Reference (Rev. 10)

EE-141: Benchmarking C Code on the ADSP-2106x and the ADSP-2116x Family of DSPs

EE-166: ADSP-2106x EPROM Overlay Support with VisualDSP++ 2.0

EE-166 Software Code

EE-132: Placing C Code and Data Modules in SHARC memory using VisualDSP++™

EE-132 Software Code

EE-128: DSP in C++: Calling Assembly Class Member Functions From C++

EE-116: SHARC Shortword DMA

EE-116 Software Code

EE-109: ADSP2106x : Using 2106x SPORT's as Timers

EE-86: Interfacing SHARC 2106x DSPs to PLX 9080 PCI Bridge Chips

EE-85: Recommended Handling of Unused SHARC Pins

EE-70: ADSP-2106x SPORT DTx pins: Is There Potential MCM Data Contention Between Different SHARCs

EE-69: Understanding and Using Linker Description Files on SHARC Processors (Rev. 2)

EE-69: Code Example (Rev 2, 01/2007)

EE-62: Accessing Short Word Memory In C

EE-47: ADSP-2106x Link Ports - Maximum Throughput

EE-46: SHARC Internal Power Measurements

EE-45: Using the ADSP-2106x/21020 EZ-ICE DBWIN Utility

EE-42: C-Programs on the ADSP-2106x

EE-110: A Quick Primer on ELF and DWARF File Formats

AN-1: SHARC Legacy Application Notes

EE-104: Setting Up Streams with the VisualDSP Debugger

EE-104 Software Code

EE-74: Analog Devices Serial Port Development and Troubleshooting Guide

EE-103: Performing Level Conversion Between 5v and 3.3v IC's

EE-37: How to Interface an LCD to the 21xx and 2106x Family DSP's

处理器使用手册 (2)

SHARC Processors: Manuals

ADSP-2106x SHARC^® User's Manual (Rev. 2.1)

Documentation Errata

集成电路异常 (1)

ADSP-21061/ADSP-21061L SHARC Anomaly List for Revision 0.1 (Rev. A)

仿真器使用手册（旧版） (2)

Apex-ICE USB Emulator Hardware Installation Guide (Rev. 6.0)

Summit-ICE PCI Emulator Hardware Installation Guide (Rev. 4)

评估板套件使用手册 (1)

ADSP-21061, 21065L and the 21160M EZ-KIT Lite^® Installation Procedure (Rev. 3.1)

软件代码及系统需求

软件工具异常

Software and Tools Anomalies Search

工具及仿真模型

BSDL模型

TXT

24 kB

ADSP-21061 SHARC Processor BSDL File 240 lead MQFP package (10/2009)

IBIS模型

TXT

ADSP-21061 IBIS Datafile (QFP Package)

[IBIS Ver]2.1,[File Rev]1.1,[Date]12/02/98

参考资料

技术文章 (1)

An Efficient Asynchronous Sampling-rate Conversion Algorithm for...

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