AD5762R:  Complete Dual, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC

The AD5762R is a dual, 16-bit, serial input, bipolar voltage output DAC that operates from supply voltages of ±11.4 V to ±16.5 V. Nominal full-scale output range is ±10 V. The AD5762R provides integrated output amplifiers, reference buffers, and proprietary power-up/power-down control circuitry. The part also features a digital I/O port, programmed via the serial interface, and an analog temperature sensor. The part incorporates digital offset and gain adjust registers per channel.

The AD5762R is a high performance converter that provides guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB, low noise, and 10 μs settling time. The AD5762R includes an on-chip 5 V reference with a reference temperature coefficient of 10 ppm/°C maximum. During power-up when the supply voltages are changing, VOUTx is clamped to 0 V via a low impedance path.

The AD5764R is based on the iCMOS® technology platform, which is designed for analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels. iCMOS enables the development of analog ICs capable of 30 V and operation at ±15 V supplies, while allowing reductions in power consumption and package size, coupled with increased ac and dc performance.

The AD5762R uses a serial interface that operates at clock rates of up to 30 MHz and is compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is programmable to either twos complement or offset binary formats. The asynchronous clear function clears all DAC registers to either bipolar zero or zero scale, depending on the coding used. The AD5762R is ideal for both closed-loop servo control and open-loop control appli-cations. The AD5762R is available in a 32-lead TQFP and offers guaranteed specifications over the −40°C to +85°C industrial temperature range (see Figure 1 for the functional block diagram).

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