|Home Analog Devices Feedback Subscribe Archives 简体中文 日本語|
Safeguard Your RS-485 Communication Networks from Harmful EMC Events
Idea In Brief
These requirements include three main transient immunity standards: electrostatic discharge, electrical fast transients, and surge.
Many EMC problems are not simple or obvious, so they must be considered at the start of the product design. Leaving these considerations to the end of the design cycle can lead to overruns in engineering budget and schedule.
This article describes each of these main transient types and presents and demonstrates three different EMC compliant solutions for three different cost/protection levels on RS-485 communication ports.
Analog Devices, Inc., and Bourns, Inc., have partnered to extend their offering of system oriented solutions by co-developing the industry’s first EMC compliant RS-485 interface design tool that provides up to Level 4 protection levels for IEC 61000-4-2 ESD, IEC 61000-4-4 EFT, and IEC 61000-4-5 surge. It gives designers the design options depending on the level of protection required and available budgets. These design tools allow designers to reduce risk of project slippage due to EMC problems by considering them at the start of the design cycle.
Some of the key features of the RS-485 that make it ideal for use in I&I communications applications are:
TIA/EIA-485-A describes the physical layer of the RS-485 interface and is normally used with a higher-level protocol, such as Profibus, Interbus, Modbus, or BACnet. This allows for robust data transmission over relatively long distances.
In real applications, however, lightning strikes, power induction and direct contact, power source fluctuations, inductive switching, and electrostatic discharge can damage RS-485 transceivers by generating large transient voltages. Designers must ensure that equipment does not only work under ideal conditions but that it will also work in the “real world.” To ensure that these designs can survive in electrically harsh environments, various government agencies and regulatory bodies have imposed EMC regulations. Compliance with these regulations gives the end user assurance that designs will operate as desired in these harsh environments.
The International Electrotechnical Commission (IEC) is the world’s leading organization that prepares and publishes international standards for all electrical, electronic, and related technologies. Since 1996, all electronic equipment sold to or within the European Community must meet EMC levels as defined in specifications IEC 61000-4-x.
The IEC 61000 specifications define the set of EMC immunity requirements that apply to electrical and electronic equipment intended for use in residential, commercial, and light industrial environments. This set of specifications includes three types of high voltage transients that electronic designers need to be concerned about for the data communication lines:
Each of these specifications defines a test method to assess the immunity of electronic and electrical equipment against the defined phenomenon. The following sections summarize each of these tests.
During testing, the data port is subjected to at least 10 positive and 10 negative single discharges with a one second interval between each pulse. Selection of the test voltage is dependent on the system end environment. The highest specified test is Level 4, which defines a contact discharge voltage of ±8 kV and an air discharge voltage of ±15 kV.
Figure 1 shows the 8 kV contact discharge current waveform as described in the specification. Some of the key waveform parameters are rise times of less than 1 ns and pulse widths of approximately 60 ns. This equates to a pulse with a total energy in the range of 10’s of mJ.
Figure 1. IEC 61000-4-2 ESD waveform (8 kV).
Electrical Fast Transients
Figure 2 shows the EFT 50 Ω load waveform. The EFT waveform is described in terms of a voltage across 50 Ω impedance from a generator with 50 Ω output impedance. The output waveform consists of a 15 ms burst of 2.5 kHz to 5 kHz high voltage transients repeated at 300 ms intervals. Each individual pulse has a rise time of 5 ns and pulse duration of 50 ns, measured between the 50% point on the rising and falling edges of the waveform. The total energy in a single EFT pulse is similar to that in an ESD pulse. The total energy in a single pulse is typically 4 mJ. Voltages applied to the data ports can be as high as 2 kV.
Figure 2. IEC 61000-4-4 EFT 50 Ω load waveforms.
These fast burst transients are coupled onto the communication lines using a capacitive clamp. The EFT is capacitively coupled onto the communication lines by the clamp rather than direct contact. This also reduces the loading caused by the low output impedance of the EFT generator. The coupling capacitance between the clamp and cable depends on cable diameter, shielding, and insulation on the cable.
The waveforms are specified as the outputs of a waveform generator in terms of open circuit voltage and short circuit current. Two waveforms are described. The 10/700 µs combination waveform is used to test ports intended for connection to symmetrical communication lines: for example, telephone exchange lines. The 1.2/50 µs combination waveform generator is used in all other cases, in particular short distance signal connections. For RS-485 ports, the 1.2/50 µs waveform is predominantly used and will be discussed in this section. The waveform generator has an effective output impedance of 2 Ω; hence, the surge transient has high currents associated with it.
Figure 3 shows the 1.2/50 µs, surge transient waveform. ESD and EFT have similar rise times, pulse widths, and energy levels; however, the surge pulse has a rise time of 1.25 µs and the pulse width is 50 µs. Additionally, the surge pulse energy can reach up to almost 90 J, which is three to four orders of magnitude larger than the energy in an ESD or EFT pulse. Therefore, the surge transient is considered the most severe of the EMC transients. Due to the similarities between ESD and EFT, the design of the circuit protection can be similar, but due to its high energy, surge must be dealt with differently. This is one of the main issues in developing protection that improves the immunity of data ports to all three transients while remaining cost effective.
Resistors couple the surge transient onto the communication line. Figure 4 shows the coupling network for a half-duplex RS-485 device. The total parallel sum of the resistance is 40 Ω. For the half-duplex device, each resistor is 80 Ω.
During the surge test, five positive and five negative pulses are applied to the data ports with a maximum time interval of one minute between each pulse. The standard states that the device should be set up in normal operating conditions for the duration of the test.
Figure 3. IEC 61000-4-5 surge 1.2/50 µs waveform.
Figure 4. Coupling/decoupling network for a half-duplex RS-485 device.
Criteria A is the most desirable with Criteria D being unacceptable. Permanent damage results in system down time and the expense of repair and replacement. For mission critical systems, Category B and Category C will also be unacceptable, as the system must operate without errors during transient events.
Figure 5 shows a typical protection scheme, which can be characterized as having primary and secondary protection. Primary protection, which diverts most of the transient energy away from the system, is typically located at the interface between the system and the environment. It is designed to remove the majority of the energy by diverting the transient to ground.
Secondary protection protects various parts of the system from any transient voltages and currents let through by the primary protection. It is optimized to ensure that it protects against these residual transients while allowing normal operation of these sensitive parts of the system. It is essential that both primary and secondary designs are specified to work together in conjunction with the system I/O to minimize the stress on the protected circuit. These designs typically include a coordinating element such as a resistance or a nonlinear overcurrent protection device between the primary and secondary protection devices to ensure that coordination occurs.
Figure 5. Protection scheme—block diagram.
RS-485 Transient Suppression Networks
The circuits shown in Figure 6 illustrate three different fully characterized EMC compliant solutions. Each solution was certified by an independent external EMC compliance test house, and each provides different cost/protection levels for the Analog Devices ADM3485E 3.3 V RS-485 transceiver with enhanced ESD protection using a selection of Bourns external circuit protection components. The Bourns external circuit protection components used consist of transient voltage suppressors (CDSOT23-SM712), transient blocking unit (TBU-CA065-200-WH), thyristor surge protectors (TISP4240M3BJR-S), and gas discharge tubes (2038-15-SM-RPLF).
Each solution was characterized to ensure that the dynamic I/V performance of the protection components protects the dynamic I/V characteristics of the ADM3485E RS-485 bus pins such that the interaction between the input/output stage of the ADM3485E and the external protection components function together to protect against the transient events.
Figure 6. Three EMC compliant ADM3485E circuits (simplified schematic, all connections not shown).
Protection Scheme 1
This solution uses the Bourns CDSOT23-SM712 transient voltage suppressor (TVS) array, which consists of two bidirectional TVS diodes optimized to protect RS-485 systems with minimal overstress while allowing the full range of RS-485 signal and common-mode excursions (–7 V to +12 V) on the RS-485 transceiver. Table 1 shows the voltage levels protected against for ESD, EFT, and surge transients.
Table 1. Solution 1 Protection Levels
A TVS is a silicon based device. Under normal operating conditions, the TVS has high impedance to ground; ideally, it is an open circuit. The protection is accomplished by clamping the overvoltage from a transient to a voltage limit. This is done by the low impedance avalanche breakdown of a PN junction. When a transient voltage larger than the breakdown voltage of the TVS is generated, the TVS clamps the transient to a predetermined level that is less than the breakdown voltage of the devices that it is protecting. The transients are clamped instantaneously (<1 ns), and the transient current is diverted away from the protected device to ground.
It is important to ensure that the breakdown voltage of the TVS is outside the normal operating range of the pins protected. The unique feature of the CDSOT23-SM712 is that it has asymmetrical breakdown voltages of +13.3 V and –7.5 V to match the transceiver common-mode range of +12 V to –7 V, therefore providing optimum protection while minimizing overvoltage stresses on the ADM3485E RS-485 transceiver.
Figure 7. CDSOT23-SM712 I/V characteristic.
Protection Scheme 2
The CDSOT23-SM712 is specifically designed for RS-485 data ports. The next two circuits build on the CDSOT23-SM712 to provide higher levels of circuit protection. The CDSOT23-SM712 provides secondary protection while the TISP4240M3BJR-S provides the primary protection. Coordination between the primary and secondary protection devices and overcurrent protection are accomplished using the TBU-CA065-200-WH. Table 2 shows the voltage levels protected against for ESD, EFT, and surge transients with this protection circuit.
Table 2. Solution 2 Protection Levels
When a transient is applied to the protection circuit, the TVS will break down, protecting the device by providing a low impedance path to ground. With large voltages and currents, the TVS must also be protected by limiting the current through it. This is done using a transient blocking unit (TBU), which is an active high speed overcurrent protection element. The TBU in this solution is the Bourns TBU-CA065-200-WH.
A TBU blocks current rather than shunting it to ground. As a series component, it reacts to current through the device rather than the voltage across the interface. A TBU is a high speed overcurrent protection component with a preset current limit and a high voltage withstand capability. When an overcurrent occurs and the TVS breaks down due to the transient event, the current in the TBU will rise to the current limiting level set by the device. At this point, the TBU disconnects the protected circuitry from the surge in less than 1 µs. During the remainder of the transient, the TBU remains in the protected blocking state, with very low current (<1 mA) passing through to the protected circuit. Under normal operating conditions, the TBU exhibits low impedance, so it has minimal impact on normal circuit operation. In blocking mode, it has very high impedance to block transient energy. After the transient event, the TBU automatically resets to its low impedance state and allows resumption of normal system operation.
Like all overcurrent protection technologies, the TBU has a maximum breakdown voltage, so a primary protection device must clamp the voltage and redirect the transient energy to ground. This is commonly done using technologies such as gas discharge tubes or solid-state thyristors, such as the totally integrated surge protector (TISP). The TISP acts as a primary protection device. When its predefined protection voltage is exceeded, it provides a crowbar low impedance path to ground, hence diverting the majority of the transient energy away from the system and other protection devices.
The nonlinear voltage-current characteristic of the TISP limits overvoltage by diverting the resultant current. As a thyristor, a TISP has a discontinuous voltage-current characteristic caused by the switching action between high and low voltage regions. Figure 8 shows the voltage current characteristic of the device. Before the TISP device switches into a low voltage state, with low impedance to ground to shunt the transient energy, a clamping action is caused by the avalanche breakdown region. In limiting an overvoltage, the protected circuitry will be exposed to a high voltage for the brief time period that the TISP device is in the breakdown region before it switches into a low-voltage protected on-state. The TBU will protect the downstream circuitry from high currents resulting from this high voltage. When the diverted current falls below a critical value, the TISP device automatically resets allowing normal system operation to resume.
As described, all three components work together in conjunction with the system I/O to protect the system from high voltage and current transients.
Figure 8. TISP switching characteristic and voltage limiting waveshape.
Protection Scheme 3
Table 3. Solution 3 Protection Levels
Predominately used as a primary protection device, a GDT provides a low impedance path to ground to protect against overvoltage transients. When a transient voltage reaches the GDT spark-over voltage, the GDT will switch from a high impedance off-state to arc mode. In arc mode, the GDT becomes a virtual short, providing a crowbar current path to ground and diverting the transient current away from the protected device.
Figure 9 shows the typical characteristics of a GDT. When the voltage across a GDT increases, the gas in the tube starts to ionize due to the charge developed across it. This is known as the glow region. In this region, the increased current flow will create an avalanche effect that will transition the GDT into a virtual short circuit, allowing current to pass through the device. During the short circuit event, the voltage developed across the device is known as the arc voltage. The transition time between the glow and arc region is highly dependent on the physical characteristics of the device.
Figure 9. GDT characteristic waveform.
The key challenge in designing EMC compliant solutions for RS-485 networks is matching the dynamic performance of the external protection components with the dynamic performance of the input/output structure of the RS-485 device
This article demonstrated three different EMC compliant solutions for RS-485 communication ports, giving the designer options depending on the level of protection required. The EVAL-CN0313-SDPZ is the industry's first EMC compliant RS-485 customer design tool, providing up to Level 4 protection levels for ESD, EFT, and surge. The protection levels offered by the different protection schemes are summarized in Table 4. While these design tools do not replace the due diligence or qualification required at the system level, they allow the designer to reduce risk of project slippage due to EMC problems at the start of the design cycle, hence reducing design time and time to market. For more information, please visit: www.analog.com/RS485emc.
Table 4. Three ADM3485E EMC Compliant Solutions
Analog Devices Interface and Isolation. http://www.analog.com/en/interface-isolation/products/index.html.
Bourns Telecom Protection Guide. www.bourns.com/data/global/pdfs/bourns_circuit_protection_selection_guide.pdf.
Electromagnetic Compatibility (EMC) Part 4-2: Testing and Measurement Techniques—Electrostatic Discharge Immunity Test (IEC 61000-4-2:2008 (Ed. 2.0)).
Electromagnetic Compatibility (EMC) Part 4-4: Testing and Measurement Techniques—Electrical Fast Transient/Burst Immunity Test (IEC 61000-4-4:2012 (Ed. 3.0)).
Electromagnetic Compatibility (EMC) Part 4-5: Testing and Measurement Techniques—Surge Immunity Test (IEC 61000-4-5:2005 (Ed. 2.0)).
GDT First Principles. www.bourns.com/pdfs/bourns_gdt_white_paper.pdf.
Marais, Hein. Application Note AN-960. RS-485/RS-422 Circuit Implementation Guide, April, 2008.
Copyright 1995- Analog Devices, Inc. All rights reserved.