|Home Analog Devices Feedback Subscribe Archives 简体中文 日本語|
Insight into digiPOT Specifications and Architecture Enhances AC Performance
Digital potentiometers (digiPOTs) provide a convenient way to adjust the ac or dc voltage or current output of sensors, power supplies, or other devices that require some type of calibration—with timing, frequency, contrast, brightness, gain, and offset adjustment being just a few of the possibilities. Digital setting avoids virtually all of the problems associated with mechanical potentiometers, such as physical size, mechanical wear out, wiper contamination, resistance drift, and sensitivity to vibration, temperature, and humidity—and eliminates layout inflexibility resulting from the need for screwdriver access.
The digiPOT can be used in two different modes: potentiometer or rheostat. In potentiometer mode, shown in Figure 1, three terminals are available; the signal is connected across Terminals A and B, while Terminal W (as in wiper) provides the attenuated output voltage. When the digital ratio-control input is all zeros, the wiper is typically connected to Terminal B.
Figure 1. Potentiometer mode.
When the wiper is hardwired to either end, the potentiometer becomes a simple variable resistor, or rheostat, as shown in Figure 2. The rheostat mode permits a smaller form factor, since fewer external pins are required. Some digiPOTs are available only as rheostats.
Figure 2. Rheostat mode.
There are no restrictions on the polarity of currents or voltages appearing at the digiPOT resistance terminals, but the amplitude of ac signals cannot exceed the power-supply rails (VDD and VSS)—and the maximum current, or current density, should be limited when the part is operated in rheostat mode, especially at lower resistance settings.
Figure 3. Signal attenuator.
Signal amplification requires an active component, typically an inverting or noninverting amplifier. Either potentiometer or rheostat mode can be used, with the appropriate gain equation.
Figure 4 shows a noninverting amplifier using the device as a potentiometer to adjust the gain via feedback. Since the fraction of output fed back, RAW/(RWB + RAW), must be equal to the input, the idealized gain is
Figure 4. Noninverting amplifier in potentiometer mode.
The gain of this circuit, inversely proportional to RAW, increases rapidly as RAW approaches zero, defining a hyperbolic transfer function. To limit the maximum gain, insert a resistor in series with RAW (and in the denominator of the gain equation).
If a linear gain relationship is desired, the rheostat mode can be used in conjunction with a fixed external resistor, as shown in Figure 5; the gain is now defined as:
Figure 5. Noninverting amplifier in rheostat mode.
For best performance, connect the lower capacitance terminal (the W pin in newer devices) to the op-amp input.
Advantages of digiPOTs for Signal Amplification
Limitations of digiPOTs for Signal Amplification
The internal architecture has evolved from the classical serial resistor array, shown in Figure 6a, to the segmented architecture, shown in 6b. The main improvement is the decreased number of internal switches required. In the first case, a serial topology, the number of switches is N = 2n, where n is the resolution in bits. With n = 10, 1024 switches are required.
Figure 6. a) Conventional architecture. b) Segmented architecture.
The proprietary (patented) segmented architecture uses a cascade connection that minimizes the total number of switches. The example of Figure 6b shows a two-segment architecture, formed by two types of blocks: MSB on the left, and LSB on the right.
The upper and lower blocks at left are strings of switches for the coarse bits (MSB segment). The block at right is a string of switches for the fine bits (LSB segment). The MSB switches establish a coarse approximation to the RA/RB ratio. Because the total resistance of the LSB string is equal to a single resistive element in the MSB strings, the LSB switches establish the fine portion of the ratio at any point of the main string. The A and B MSB switches are complementary coded.
The number of switches in the segmented architecture is:
where n is the total number of bits and m the number of bits of resolution in the MSB word. For example, if n = 10 and m = 5, 96 switches are required.
The segmented scheme requires fewer switches than the conventional string:
In this example, the savings would be
In both architectures, switches are responsible for choosing among the different resistance values, making it important to understand the ac error sources in an analog switch. These CMOS (complementary-metal-oxide semiconductor) switches are made up of P-channel and N-channel MOSFETs in parallel. This basic bilateral switch maintains a fairly constant resistance (RON) for signals up to the full supply rails.
Figure 7. CMOS switch model.
CDS = drain-source capacitance; CD = drain-gate + drain-bulk capacitance; CS = source-gate + source-bulk capacitance.
The transfer relationship is defined in the equation below, where these assumptions have been applied:
The transfer equation has many factors and is somewhat code-dependent, so the following further assumptions are used to simplify the equation
The CDS contribution adds a zero in the transfer equation, but since this occurs typically at much higher frequency than the pole, an RC low-pass filter is the dominant response. A good approximation of the simplified equati on is:
and the bandwidth (BW) is defined as:
where CL is the load capacitance.
The BW is code dependent, and the worst case is when the code is at half scale, a digital value of 29 = 512 for the AD5292 and 27 = 128 for the AD5291 (see Appendix). Figure 8 shows the low-pass filtering effect as a function of code for various nominal resistance and load capacitance values.
Figure 8. Maximum bandwidth vs. load capacitance for various resistance values.
The parasitic track capacitance of the PC board should be taken into account, otherwise the maximum BW will be lower than expected; the track capacitance can be calculated straightforwardly as
For example, assuming FR4 board material with two signal layers and power/ground planes, εR = 4, track length = 3 cm, width = 1.2 mm, and distance between layers = 0.3 mm; the total track capacitance is about 4 pF.
Figure 9. Distortion.
The RON of a switch is quite small when compared with the resistance of a single internal passive resistor, and its variation over the signal range is even smaller. Figure 10 shows a typical on-resistance characteristic.
Figure 10. CMOS resistance.
The resistance curve does depend on the supply voltage rails; the internal switches have the lowest RON variation at maximum supply voltage. If the supply voltage is decreased, the RON variation, and hence the nonlinearity, increases. Figure 11 compares RON variation at two supply levels for a low-voltage digiPOT.
Figure 11. Switch resistance variation vs. supply voltage.
The THD depends on multiple factors and is thus hard to quantify, but assuming a 10% variation in RON, the following equation can be used as a rough approximation:
As a general rule, the higher the nominal digiPOT resistance (RPOT), the better the THD, as the denominator is larger.
One approach is to use a dual supply and simply ground the potentiometer to the power-supply common. The signal can then have a positive-negative swing. Another way, if a single supply is required, or the particular digiPOT doesn’t support dual supply, is to add an offset voltage of VDD/2 to the ac signal. This offset voltage must be added at both resistor terminals, as shown in Figure 12.
Figure 12. Single-supply ac signal conditioning.
If a signal amplifier is required, an inverting amplifier, with a dual supply, as shown in Figure 13, is preferred over the noninverting amplifier for two reasons:
Figure 13. Adjustable amplification using a digiPOT with an inverting amplifier.
256-/1024-Position Digital Potentiometers Are 1% Accurate,
Figure 14. AD5291/AD5292 functional block diagram.
Copyright 1995- Analog Devices, Inc. All rights reserved.