14-Output Clock Generator with Integrated 2.8 GHz VCO
The AD9516-0 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.
The AD9516-0 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.
Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.
The AD9516-0 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9516-0 is specified for operation over the industrial range of −40°C to +85°C.
- Low jitter, low phase noise clock distribution
- 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4
- Forward error correction (G.710)
- Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
- High performance wireless transceivers
- ATE and high performance instrumentation
1 AD9516 is used throughout to refer to all the members of the AD9516 family. However, when AD9516-0 is used it is referring to that specific member of the AD9516 family.
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Product Selection Guide
RF Source Booklet
RF IC Product Overview
Single-Chip Clock Generator with 14-Channel Distribution Solves Timing...
(Analog Dialogue, Volume 41, August, 2007)
Low-power direct digital synthesizer cores enable high level of integration
Improved DDS Devices Enable Advanced Comm Systems
by Valoree Young, Analog Devices
(Electronic Products, September 2006)
ADI Buys Korean Mobile TV Chip Maker
(EE Times, 6/7/2006)
Design A Clock-Distribution Strategy With Confidence
by Demetrios Efstathiou (Electronic Design, April 27, 2006)
Clock Requirements For Data Converters
(Electronic Design, 2/2005)
Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
... Much of your system's performance depends on jitter specifications, so careful assessment is critical.
Rarely Asked Questions
How can I improve system performance when using multiple clocks?
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Didn't find what you were looking for?
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.