The ADP5024 combines two high performance buck regulators and one low dropout (LDO) regulators in a small, 24-lead 4 mm x 4 mm LFCSP to meet demanding performance and board space requirements.
The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. When the MODE pin is set high, the buck regulators operate in forced PWM mode. When the MODE pin is set low, the buck regulators operate in PWM mode when the load current is above a predefined threshold. When the load current falls below a pre-defined threshold, the regulator operates in power save mode (PSM), improving the light load efficiency.
The two bucks operate out of phase to reduce the input capacitor requirement. The low quiescent current, low dropout voltage, and wide input voltage range of the LDO extends the battery life of portable devices. The ADP5024 LDO maintains power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage.
Regulators in the ADP5024 are activated though dedicated enable pins. The default output voltages can be either externally set in the adjustable version or factory programmable to a wide range of preset values in the fixed voltage version.
|Title||Content Type||File Type|
|ADP5024: Dual 3 MHz, 1200 mA Buck Regulators with One 300 mA LDO Data Sheet (Rev E, 05/2013) (pdf, 926 kB)||Data Sheets|
|UG-271: Evaluation Board for the ADP5023/ADP5024/ADP5034/ADP5037 Micro Power Management Unit (PMU) (pdf, 442 kB)||User Guides|
Integrated Power Solutions for Xilinx FPGAs
(pdf, 2253 kB)
Combining multiple switching regulators and LDOs into a single package enables very small, flexible, highly efficient power management solutions for powering FPGAs.
|Integrated Power Solutions for Altera FPGAs (pdf, 2460 kB)||Solutions Bulletins|
|Glossary of EE Terms||Glossary||HTML|
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