Universal Serial Bus (USB) Peripheral Isolator Circuit
- Isolate directly in the USB D+ and D− lines allowing the use of existing USB infrastructure in microprocessors.
- Implement an automatic scheme for data flow of control that does not require external control lines.
- Provide medical grade isolation.
- Allow a complete peripheral to meet the USB-IF certifi-cation standards.
- Support full speed (12 Mbps) and low speed (1.5 Mbps) signaling rates.
- Support flexible power configurations.
The application circuit shown is typical of many medical and industrial applications.
Figure 1. USB Peripheral Isolator Circuit
The ADuM4160 has several options for power, speed, and protection that must be determined. The first is the speed at which the peripheral runs. Peripheral devices run at one of three speeds: low (1.5 Mbps), full (12 Mbps), and high speed (480 Mbps). The ADuM4160 does not support high speed operation and blocks handshaking signals that are used to negotiate that speed. High speed mode starts as a full speed configuration, and the peripheral requests high speed support through a process called a high speed chirp. The ADuM4160 ignores the high speed chirp; therefore, the request for high speed operation is never passed on to the host, and the peripheral continues to work at full speed.The speed of the peripheral on the USB bus is either low speed or full speed. The particular peripheral determines the speed required, and the ADuM4160 must be set to match this speed via the state of the SPU and SPD pins. In the current schematic, the SPU and SPD pins are tied to the internally regulated 3.3 V power supplies, VDD1 and VDD2, setting the part for full speed operation.
Power can be provided as 5 V through the VBUSx pins, and the 3.3 V signaling voltage is created by an internal 3.3 V regulator at the VDDx pin. Alternatively, the 3.3 V power can also be provided to VBUSx and VDDx, and the part uses the external supply directly, disabling the internal regulator.
This option was provided to allow the ADuM4160 to run either from a 5 V USB cable or from an available 5 V or 3.3 V rail supplied by a peripheral. In the circuit shown, it was connected to accept 5 V from each side, and the internal regulators are active.
The ADuM4160 has an option to delay application of the upstream pull-up under control of the peripheral. This function is controlled by the PIN input. In this application, the PIN input is jumpered high so that the upstream pull-up is applied as soon as peripheral power is applied. In other applications, it can be connected to a GPIO pin of a controller, a fixed delay circuit can be applied, or it can be connected as shown in this circuit. It is the designer’s choice how to use this functionality.
Protection devices are included in this circuit. These were chosen from manufacturers that have a wide variety of components available, and the particular components were chosen to allow them to be replaced by 0 Ω shorts, thereby removing them from the circuit. The choice of protection should be reviewed by the designer and can range from no external protection to a full complement of transient suppressors and filter elements. The circuit elements included in this circuit show a typical high protection configuration.
When the circuit is functioning, packets are detected and data is shuttled from one side of the isolation barrier to the other. Data shown in Figure 2 and Figure 3 demonstrates a typical full speed transaction both as time domain data and as an eye diagram. Features to note in the real-time data are the passive idle state at the start of the packet, which transitions to a driven J, and then the end of the packet at the end of the transaction showing as a single-ended zero state followed by idle J. It is the automatic flow of control and the handling of these special logic states that make the ADuM4160 unique in the marketplace.
The data shown in Figure 2 and Figure 3 below are generated as part of the USB-IF qualification process. Figure 2 shows a test data packet from the ADuM4160 upstream port to the host. Portions to note are the leading idle state where the passive resistor network holds an idle J state. The center portion of the packet is a mix of J and K states. The right side of the packet is an EOP (end of packet) marker, which is a single-ended 0 followed by a driven J, which transitions to an idle J.
Figure 2. Full Speed Test Packet Traffic Driven By the Upstream ADuM4160 Port
The following are applicable test references:
- Upstream full speed signal quality test reference—USB 2.0 Specification, Section 7.1.11., Section 22.214.171.124.
- Upstream full speed rise time test reference—USB 2.0 Specification, Section 7.1.11., Section 126.96.36.199.
- Upstream full speed fall time test reference—USB 2.0 Specification, Section 7.1.11., Section 188.8.131.52.
Figure 3 is a full speed eye diagram showing that the ADuM4160 provides an adequate open eye, staying well out of the keep out region. Similar data is also taken for low speed evaluation.
Figure 3. Full Speed Eye Diagram Showing Exclusion Zone
A photo of a typical application circuit is shown in Figure 4. The ADuM4160 evaluation board (left side of photo) is connected to the evaluation board for the AD7991 4-channel, 12-/10-/8-bit ADC with I2C compatible interface. The ADC evaluation board acts as a peripheral, which interfaces to a PC (for test and evaluation of the ADC) via the USB port. This provides total isolation between the ADuM4160 USB port and the ADC evaluation board.
Because of the fast edge speeds associated with this circuit, excellent layout, decoupling, and grounding techniques must be employed in order to pass system EMI/RFI tests. See Tutorial MT-031, Tutorial MT-101, and the AN-0971 Application Note for guidance. A complete design support package for this circuit note can be found at http://www.analog.com/CN0160-DesignSupport.
Figure 4. Photo of ADuM4160 USB Evaluation Board Connected to USB Port of AD7991 Evaluation Board
The following equipment is needed: a PC with Windows® XP or Vista, a USB data port connection, the ADuM4160 evaluation board isolation adapter, the EVAL-7991EBZ evaluation board and AD7991 evaluation software, two USB cables, and a high speed digital oscilloscope.
In addition to the circuit and schematic of the test setup described in this Circuit Note, details regarding the ADuM4160 evaluation board isolation adapter, including schematics, Gerber’s, and bill of materials, are available at http://www.analog.com/CN0160-DesignSupport.
Functional Block Diagram
See Figure 1 for the schematic diagram and other information regarding the described test setup.
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