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AD9878:  Low Cost, 3.3 V, CMOS Mixed Signal Front End (MxFE®) for Broadband Applications

Product Details


The AD9878 is a single-supply cable modem/set-top box mixed-signal front end. The device contains a transmit path interpolation filter, a complete quadrature digital upconverter, and transmit DAC. The receive path contains dual, 12-bit ADCs and a 10-bit ADC. All internally required clocks and an output system clock are generated by the PLL from a single crystal oscillator or clock input.

The transmit path interpolation filter provides an upsampling factor of 16 x with an output signal bandwidth up to 5.8 MHz. Carrier frequencies up to 65 MHz with 26 bits of frequency tuning resolution can be generated by the direct digital synthesizer (DDS). The transmit DAC resolution is 12 bits and can run at sampling rates as high as 232 MSPS. Analog output scaling from 0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when reduced output levels are required.

The 12-bit ADCs provide excellent undersampling performance, allowing this device to deliver better than 10 ENOBs with IF inputs up to 70 MHz. The 12-bit IF ADCs can sample at rates up to 29 MHz, allowing them to process wideband signals.

The AD9878 includes a programmable sigma-delta DAC, which can be used to control an external component such as a variable gain amplifier (VGA)or a voltage controlled tuner. The AD9878 also integrates a CA port that enables a host processor to interface with the AD8321/AD8323 or AD8322/AD8327/AD8328 programmable gain amplifier (PGA) cable drivers via the MxFE serial port (SPORT).

The AD9878 is available in a 100-lead LQFP package. The AD9878 is specified over the extended industrial (–40 °C to +85 °C) temperature range.

FEATURES and BENEFITS

  • Low Cost 3.3 V CMOS MxFE® for Broadband Applications
  • DOCSIS, EURO-DOCSIS, DVB, DAVIC Compliant
  • 232 Mhz Quadrature Digital Upconverter
  • 12-Bit Direct IF DAC (Txdac+®)
  • Up To 65 Mhz Carrier Frequency DDS
  • Programmable Sampling Clock Rates
  • Analog Tx Output Level Adjust
  • Dual 12-Bit, 29 MSPS Direct
    IF ADCs with Video Clamp Input
  • 10-Bit, 29 MSPS Sampling ADC
  • 8-Bit Sigma-Delta Auxiliary DAC
  • Direct Interface To AD8321/AD8323 or AD8322/AD8327 PGA Cable Driver

Functional Block Diagram for AD9878

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Documentation

Title Content Type File Type
AD9878: Mixed-Signal Front End for Broadband Applications Data Sheet (Rev A, 03/2005) (pdf, 749 kB) Data Sheets PDF
AN-851: A WiMax Double Downconversion IF Sampling Receiver Design  (pdf, 262 kB) Application Notes PDF
MS-2210: Designing Power Supplies for High Speed ADC  (pdf, 327 kB) Technical Articles PDF
RAQs index Rarely Asked Questions HTML
Glossary of EE Terms Glossary HTML

Evaluation Kits & Symbols & Footprints

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