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AD9864:  IF Digitizing Subsystem

Product Details

The AD9864 is a general-purpose IF subsystem that digitizes a low level 10 MHz to 300 MHz IF input with a signal bandwidth ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9864 consists of a low noise amplifier (LNA), a mixer, a band-pass Σ-Δ analog-to-digital converter (ADC), and a decimation filter with programmable decimation factor. An automatic gain control (AGC) circuit gives the AD9864 12 dB of continuous gain adjustment. Auxiliary blocks include both clock and LO synthesizers.

The high dynamic range of the AD9864 and inherent antialiasing provided by the band-pass Σ Δ converter allow the device to cope with blocking signals up to 95 dB stronger than the desired signal. This attribute often reduces the cost of a radio by reducing IF filtering requirements. Also, it enables multimode radios of varying channel bandwidths, allowing the IF filter to be specified for the largest channel bandwidth.

The SPI® port programs numerous parameters of the AD9864, allowing the device to be optimized for any given application. Programmable parameters include synthesizer divide ratios, AGC attenuation and attack/decay time, received signal strength level, decimation factor, output data format, 16 dB attenuator, and the selected bias currents.

The AD9864 is available in a 48-lead LFCSP package and operates from a single 2.7 V to 3.6 V supply. The total power consumption is typically 56 mW and a power-down mode is provided via serial interfacing.


  • Multimode Narrow-Band Radio Products
    - Analog/Digital UHF/VHF FDMA Receivers
  • Portable and Mobile Radio Products
  • SATCOM Terminals


  • 10 MHz to 300 MHz Input Frequency
  • 6.8 kHz to 270 kHz Complex Output Signal Bandwidth
  • 7.5 dB SSB NF
  • –7.0 dBm IIP3
  • 95 dB Dynamic Range with 12 dB Continous AGC Range Enabled
  • -18 or -30 dBm max IF Input with AGC Disabled
  • 16 dB Front End Attenuator
  • LO and Sampling Clock Synthesizers
  • Baseband I/Q 16-Bit (or 24-Bit) Serial Digital Output
  • Programmable Decimation Factor, Output Format, AGC, and Sythesizer Settings
  • 2.7 V to 3.6 V Supply Voltage

Functional Block Diagram for AD9864


Title Content Type File Type
AD9864: IF Digitizing Subsystem Data Sheet (Rev 0, 08/2003) (pdf, 1984 kB) Data Sheets PDF
MS-2735: Maximizing the Dynamic Range of Software-Defined Radio  (pdf, 351 kB) Technical Articles PDF
MS-2210: Designing Power Supplies for High Speed ADC  (pdf, 327 kB) Technical Articles PDF
Get More Mixed Signal Integration For Less Risk, Cost, and Size Overview HTML
RAQs index Rarely Asked Questions HTML
Glossary of EE Terms Glossary HTML

Design Tools,Models,Drivers & Software

Title Content Type File Type
AD9864 IBIS Models IBIS Models HTML

Evaluation Kits & Symbols & Footprints

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Price, packaging, availability

AD9864 Model Options
Price Table Help

The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.

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