The AD7887 is a high speed, low power, 12-bit analog-to-digital converter (ADC) that operates from a single 2.7 V to 5.25 V power supply. The AD7887 is capable of 125 kSPS throughput rate. The input track-and-hold acquires a signal in 500 ns and features a single-ended sampling scheme. The output coding for the AD7887 is straight binary, and the part is capable of converting full power signals of up to 2.5 MHz.
The AD7887 can be configured for either dual- or single-channel operation via the on-chip control register. There is a default single-channel mode that allows the AD7887 to be operated as a read-only ADC. In single-channel operation, there is one analog input (AIN0) and the AIN1/VREF pin assumes its VREF function. This VREF pin allows the user access to the part’s internal 2.5 V reference, or the VREF pin can be overdriven by an external reference to provide the reference voltage for the part. This external reference voltage has a range of 2.5 V to VDD. The analog input range on AIN0 is 0 to VREF.
In dual-channel operation, the AIN1/VREF pin assumes its AIN1 function, providing a second analog input channel. In this case, the reference voltage for the part is provided via the VDD pin. As a result, the input voltage range on both the AIN0 and AIN1 inputs is 0 to VDD.
CMOS construction ensures low power dissipation of typically 2 mW for normal operation and 3 μW in power-down mode. The part is available in an 8-lead, 0.15-inch-wide narrow body SOIC and an 8-lead MSOP package.Product Highlights
|Title||Content Type||File Type|
|AD7887: 2.7 V to 5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead MSOP Data Sheet (Rev E, 09/2014) (pdf, 452 kB)||Data Sheets|
|CN-0189: Tilt Measurement Using a Dual Axis Accelerometer (pdf, 285 kB)||Circuit Note|
|CN-0150: Software Calibrated, 1 MHz to 8 GHz, 70 dB RF Power Measurement System Using the AD8318 Logarithmic Detector (pdf, 250 kB)||Circuit Note|
|UG-674: Evaluating the AD7887 12-Bit, Analog-to-Digital Converter (pdf, 2260 kB)||User Guides|
Finding the Needle in a Haystack: Measuring small differential voltages in the presence of large common-mode voltages
(Analog Dialogue, Vol. 34, No. 1, January-February, 2000)
How to Save Power in Battery Applications Using the Power-Down Mode in an ADC
by Mercedes Casamayor and Claire Croke, Analog Devices, Inc. (Analog Dialogue, Vol. 37, 9/2003)
|MS-2210: Designing Power Supplies for High Speed ADC (pdf, 327 kB)||Technical Articles|
|RAQs index||Rarely Asked Questions||HTML|
|Glossary of EE Terms||Glossary||HTML|
|Title||Content Type||File Type|
|CN0150 FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design||FPGA HDL||HTML|
|CN-0189 FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design||FPGA HDL||HTML|
|BeMicro FPGA Project for CN0150 with Nios driver||FPGA HDL||HTML|
|AD7887 - Microcontroller No-OS Driver||Device Drivers||HTML|
|AD7887 IIO ADC Linux Driver (Wiki Site)||Device Drivers||HTML|
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