ADCLK925

RECOMMENDED FOR NEW DESIGNS

Ultrafast SiGe ECL Clock/Data Buffers

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Part Details

  • 95 ps propagation delay
  • 7.5 GHz toggle rate
  • 60 ps typical output rise/fall
  • 60 fs random jitter (RJ)
  • On-chip terminations at both input pins
  • Extended industrial temperature range: −40°C to +125°C
  • 2.5 V to 3.3 V power supply (VCC − VEE)
ADCLK925
Ultrafast SiGe ECL Clock/Data Buffers
ADCLK925 Functional Block Diagram ADCLK925 Pin Configuration
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Tools & Simulations

ADIsimCLK Design and Evaluation Software

ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.

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ADCLK925 IBIS Model 1


Reference Designs

Block Diagram of the EVAL-CN0290-SDPZ
CN0290 Circuits from the lab

Extending the Low Frequency Range of a High Performance Phase Locked Loop

Features and Benefits

  • Phase locked loop with extended low frequency range
  • LO down to 10MHz, RF down to 100MHz
  • Low distortion and phase noise
CN0290
Extending the Low Frequency Range of a High Performance Phase Locked Loop
Block Diagram of the EVAL-CN0290-SDPZ

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