Improving Linearity by Using Absorptive Filters

Introduction:

When driving a direct sampling high speed ADC, the most likely place to degrade the performance is the interface between the final amplifier and the ADC. With any direct sampling ADC there will be nonlinear charge produced in the sampling process. This charge is reflected into the input network each time the sampling switches close. If these are left un-attenuated they can be reflected back to the ADC and re-sampled, degrading the simple distortion or intermodulation distortion of the ADC. The input network of the ADC should be as close to 50Ω as possible to allow for the maximum absorption of this nonlinear charge. Using a highly absorptive filter can improve the SFDR by suppressing the nonlinear tones created in the sampling process.

Using the LTC6409 to drive the AD9265

The LTC6409 is a differential amplifier with excellent linearity making it an ideal driver for the AD9265. The AD9265 is a 16-bit 125Msps high performance ADC with better than 77dB SNR and 89dB SFDR at 100MHz. These specifications can quickly degrade by poor design choices when designing the input network. In nearly all cases a filter is required between the ADC and amplifier to reduce the wideband noise of the final amplifier. Both the design and layout of this filter are critical. The filter should be absorptive so that high frequency non-linearities from the sampling process are absorbed into 50Ω termination and not allowed to be reflected back into the ADC input. Figure 1 shows an absorptive filter network that can be used between the LTC6409 and AD9265. Figure 2 shows the filter response. The purpose of this filter is not to be highly selective but simply to attenuate the wideband noise of the amplifier and nonlinearities of sampling process. At high frequency the inductors become opens and the capacitors become shorts which directs the high frequency content of the sampling process to 50Ω termination resistors. If the traces are routed at 50Ω there will not be any return reflections and the SFDR of the ADC will not degrade.

Figure 1: Filter network between the LTC6409 and the AD9265

Figure 1. Filter network between the LTC6409 and the AD9265

Figure 2: Simulated Filter response for the circuit shown in figure 1

Figure 2. Simulated Filter response for the circuit shown in figure 1

Another potential source of distortion is an asymmetrical layout of the input network. With an ideal layout, the differential nature of the signals allows excellent common mode rejection and very good 2nd harmonic distortion. Any deviation from perfect symmetry will cause a mismatch in the differential signals which will manifest itself as 2nd order harmonic distortion. Even a simple design decision to flood copper closer on one side of the differential pair than the other side can cause a difference in ground current in the adjacent ground planes. This adds distortion to the system. Absolute symmetry is required for maximum performance.

Figure 3 shows the PCB layout of the LTC6409 driving the AD9265 and the filter network. Care was taken to preserve the symmetry of the network as well as position the absorptive elements to maximize their effectiveness. The first set of absorptive elements are positioned so that any high frequency products are immediately absorbed. The main signal path meanders around the grounded copper until it gets to the second set of absorptive elements and finally to the source termination at the amplifier. This network maximizes the performance possible from the LTC6409 and the AD9265.

Figure 3: Layout of the LTC6409 and AD9265

Figure 3. Layout of the LTC6409 and AD9265

Results

To compare the performance of the LTC6409 and AD9265, a board was designed to connect to the PScope software via the DC890. The absorptive filter in figure 1 and a reflective filter in figure 4 were populated and tested over frequency. The AD9265 was clocked with a 125Msps low jitter clock and the LTC6409 was driven with a filtered sinusoidal signal from 48.1 to 178.1MHz. The SNR and SFDR were recorded with PScope. A sample data collection can be seeing in figure 5. The comparison of SNR and SFDR with the absorptive and reflective filters are shown in figures 6 and 7. The SFDR is consistently better with the absorptive network, at some points it is up to 10dB better. The SNR is also consistently better until very high input frequencies when the SNR is dominated by other factors.

Figure 4: Reflective filter used between LTC6409 and AD9265

Figure 4. Reflective filter used between LTC6409 and AD9265

Figure 5: Sample data collection from PScope. 58.1MHz being sampled at 125Msps

Figure 5. Sample data collection from PScope. 58.1MHz being sampled at 125Msps

Figure 6: SNR comparison between absorptive and reflective filters

Figure 6. SNR comparison between absorptive and reflective filters

Conclusion:

With an absorptive network, the performance of the system improves over a reflective network. The excellent performance of the LTC6409 and AD9265 was degraded when a reflective network was used. The results are clear with the LTC6409 and AD9265 but the practice of using highly absorptive and symmetrical input networks can be applied to any direct sampling ADC and differential amplifier. By focusing on the interface between the amplifier and ADC, maximum performance can be realized.

Об авторах

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Clarence Mayott

Clarence Mayott is a mixed signal application section leader with over 10 years of experience at Linear Technology.

Beginning with the DC1151, a demo board for the LTC2246H, Clarence has designed nearly all of the high speed ADC demo boards for Linear Technology. These boards have been used for evaluation purposes in a wide range of applications. He designed demo boards with complete signal chains combining amplifiers and ADC combinations to help the end customer evaluate systems more easily. He also designed companion boards, including clock and signal source boards, to help facilitate the evaluation of high speed ADC demo boards. Clarence manages the continued development of PScope, the software used for various pipeline and SAR ADCs.

His expertise in design and layout of demo boards allows him to instruct customers on how to implement high speed ADCs into their own designs. He has worked on many technical areas, including medical, automotive and communications. His experience allows him to see schematic errors, minute layout errors, and other design flaws in designs.

With the release of the LTC2000, Clarence has expanded his knowledge base to include high speed DACs and waveform generation in addition to high speed ADCs. As an application section leader he oversees the continued development of LTDACGen a new software tool for generating complex waveforms for high speed DACs.

He has given technical trainings both within Linear Technology and to potential customers describing how to implement proper signal chains from the antenna through the FPGA.

He received an M.S. in Electrical Engineering from Santa Clara University and a B.S. degree in Electrical Engineering from California State University Polytechnic San Luis Obispo.