Аэрокосмические и оборонные радарные системы


ADI Cyber Security Solutions
ADI является лидером в области кибербезопасности и предлагает свой богатый опыт работы, начиная от встраиваемых систем шифрования и управления ключами до проектирования на уровне системы.

Благодаря широкому ассортименту продукции и возможностям проектирования на заказ ADI предоставляет комплексные решения, предназначенные для преобразования радиочастотных сигналов в цифровой вид, для широкого спектра коммерческих и военных радиолокационных систем. Высокое разрешение наших АЦП / ЦАП и точность модулей тактирования и синтеза сигналов, смесителей и фильтров обеспечивают высокое отношение сигнал-шум, необходимое для точности обнаружения и баланса элементов активной фазированной антенной решётки. Наши решения следующего поколения на основе КМОП и кремний-германия (SiGe), а также современные подсистемы поддерживают более высокую интеграцию, позволяя реализовать новые системные концепции и многофункциональные системы.
Analog Devices признает необходимость использования усилителей высокой мощности с высоким КПД для увеличения расстояния приема и передачи сигналов, уменьшения количества каскадов усиления и, вследствие этого, уменьшения размеров модулей приема и передачи. Успехи в области процессов производства полупроводников, такие как освоение нитрид галлиевой (GaN) технологии, позволили вытеснить традиционные усилители на лампе бегущей волны усилителями и смесителями ADI, которые занимают меньшую площадь на печатной плате, требуют меньшее охлаждение и при этом более надежны.
Узнайте, как современные ВЧ и СВЧ технологии ADI позволяют добиться наилучших рабочих характеристик радарных систем.
Сигнальные цепочки
(4)
Интерактивные сигнальные цепочки

Типовые проекты
CN0321

This circuit provides a complete, fully isolated, analog output channel suitable for programmable logic controllers (PLCs) and distributed control system (DCS) modules that require standard 4 mA to 20 mA HART®1-compatible current outputs and unipolar or bipolar output voltage ranges. It provides a flexible building block for channel-to-channel isolated PLC/DCS output modules or any other industrial application that requires a fully isolated analog output. The circuit also includes external protection on the analog output terminals.
The AD5422 16-bit digital-to-analog converter (DAC) is software configurable and provides all the necessary current and voltage outputs.
The AD5700-1, the industry’s lowest power and smallest footprint HART-compliant IC modem, is used in conjunction with the AD5422 to form a complete HART-compatible 4 mA to 20 mA solution. The AD5700-1 includes a precision internal oscillator that provides additional space savings, especially in channel-to-channel isolated applications.
PLC/DCS solutions must be isolated from the local system controller to protect against ground loops and to ensure robustness against external events. Traditional solutions use discrete ICs for both power and digital isolation. When multichannel isolation is needed, the cost and space of providing discrete power solutions becomes a big disadvantage. Solutions based on optoisolators typically have reasonable output regulation but require additional external components, thereby increasing board area. Power modules are often bulky and can provide poor output regulation. The circuit in Figure 1 uses the ADuM347x family of isolators and power regulation circuitry along with associated feedback isolation. External transformers are used to transfer power across the isolation barrier.
The ADuM3482 provides the UART signal isolation for the AD5700-1.
The ADP2441, 36 V step-down dc-to-dc regulator, accepts an industrial standard 24 V supply, with wide tolerance on the input voltage. It steps this down to 5 V to power all controller side circuitry. The circuit also includes standard external protection on the 24 V supply terminals, as well as protection against dc overvoltage of +36 V down to −28 V.
1 HART is a registered trademark of the HART Communication Foundation.

Применяемые компоненты
AD5422
Single Channel, 16-Bit, Current Source & Voltage Output DAC, HART Connectivity
ADP2441
Синхронный понижающий стабилизатор постоянного напряжения, 36 В/1 А
ADUM3471
Isolated Switching Regulators (3/1 Channel Directionality)
AD5700-1
Малопотребляющий HART модем с прецизионным внутренним генератором
ADUM3482
Small, 3.75 kV RMS Quad Digital Isolators (2/2 Channel Directionality)
Области применения
CN0228

The high performance PLL synthesizer circuit in Figure 1 requires 28 V for the tuning voltage of an octave range (1 GHz to 2 GHz) voltage controlled oscillator (VCO). An efficient boost converter provides this voltage, and the circuit operates on a single 5 V supply with no measurable degradation on the phase noise due to the dc-to-dc boost converter.

The circuit is optimized for PLLs that use octave range VCOs to provide a wide range of output frequencies. This type of VCO requires a high tuning voltage that may not be available in most systems that operate on relatively low supply voltages.
For example, the VCO in the circuit (Synergy DCYS100200-12) covers the 1 GHz to 2 GHz frequency band; however, to use the full octave range available, a tuning voltage of 0 V to 28 V is required.
There are two ways to supply this tuning voltage. The traditional technique uses an active loop filter with the amplifiers supplied by the high voltage supply. The optimum technique, however, uses a high voltage PLL synthesizer, such as the ADF4150HV, where the PLL provides the tuning voltage without the need for an active loop filter.
Although both solutions require a high voltage supply, the ADF4150HV eliminates the need for an active loop filter, which not only reduces component count and costs, but also reduces the distortion and phase noise associated with the amplifiers in the active filter. The high voltage supply is connected to the VP pin of the ADF4150HV charge pump, and any ripple on the supply is isolated from the VCO input by the passive loop filter.
The decreased sensitivity to distortion and ripple allows an efficient dc-to-dc boost converter to generate the 28 V supply for the charge pump supply pin (VP) of the ADF4150HV from a 5 V supply. See " Power Management Design for PLLs," Analog Dialogue, 45-09, for a complete discussion on powering PLLs.
Figure 1 shows an industry-leading solution using the ADF4150HV and the ADP1613 boost converter. Total board area for the boost regulator is only 43 mm2, and the ADP1613 is available in an 8-lead MSOP package.
Применяемые компоненты
Области применения
CN0239

The circuit shown in Figure 1 is a 10 MHz to 6 GHz wideband active mixer with a direct interface to a frequency synthesizer-based low phase noise local oscillator (LO).
This circuit offers an optimum solution that is attractive in wideband applications that require frequency conversion to higher or lower frequencies. The two-chip circuit covers a broad LO frequency range from 35 MHz to 4400 MHz. The LO interface is simple and glueless, eliminating the need for a balun, matching network, and LO buffer. In addition, the mixer bias adjust function allows optimization of IP3, noise figure, and supply current based on the application requirements or on the size of the input signal.

Применяемые компоненты
Области применения
CN0290

The circuit shown in Figure 1 is a high performance phase locked loop (PLL) that uses high speed clock buffers and low noise LDOs to maintain low phase noise even at low reference and RF frequencies.

For example, the minimum reference frequency and the RF input frequency of a number of Analog Devices PLLs, such as the ADF4106, are specified for 20 MHz and 500 MHz, respectively. The frequency range can be lowered to a 10 MHz reference frequency and a 100 MHz RF input using the additional clock buffers as in Figure 1.
Применяемые компоненты
ADCLK905
SiGe буферы сигналов синхронизации/данных формата ECL с крайне высоким быстродействием
ADCLK925
SiGe буферы сигналов синхронизации/данных формата ECL с крайне высоким быстродействием
ADF4106
Синтезатор частот с ФАПЧ
ADP150
Линейный КМОП стабилизатор с крайне низким шумом, выходной ток 150 мА
ADP7102
КМОП LDO-стабилизатор с низким шумом, 20 В/300 мА
Области применения
Связь
CN0390

The automatic gain control (AGC) circuit is useful in multiple applications such as amplitude stabilization of a synthesizer, controlling output power in a transmitter, or optimizing dynamic range in a receiver. The circuit shown in Figure 1 uses the ADL6010 detector, along with the HMC985A voltage variable attenuator (VVA) and the HMC635 RF amplifier, to provide automatic gain control over a wide range of input frequencies (20 GHz to 37.5 GHz) and amplitude. Circuit performance, as measured by the AGC figures of merit described in this circuit note, are very good between 20 GHz and 30 GHz. The overall gain of the circuit falls off above 30 GHz. However, improvements can be made over narrow bands by using matching techniques not explored in this circuit note.
The AGC circuit has applications in microwave instrumentation and radar-based measurement systems.


Применяемые компоненты
HMC635LC4
GaAs PHEMT MMIC Driver Amplifier, 18 - 40 GHz
HMC985ALP4KE
GaAs MMIC Voltage - Variable Attenuator, 10 - 40 GHz
ADA4077-1
Прецизионный одноканальный усилитель с малыми напряжением смещения и дрейфом, 4 МГц, 7 нВ/√Гц, 30 В
ADL6010
Детектор мощности с коротким временем отклика, динамический диапазон 45 дБ, диапазон частот 500 МГц - 40 ГГц
Области применения
Авиация, космос, оборона
- Радиоэлектронное наблюдение и средства радиоэлектронной борьбы
- Военная радиосвязь
- Аэрокосмические и оборонные радарные системы
CN0364

The circuit shown in Figure 1 provides a complete, fully isolated, highly flexible, quad channel analog input system suitable for programmable logic controllers (PLCs) and distributed control system (DCS) applications that require multiple voltage inputs and HART-compatible, 4 mA to 20 mA current inputs.
The analog input circuit is designed for group isolated industrial analog inputs and can support voltage and current input ranges including ±5 V, ±10 V, 0 V to +5 V, 0 V to +10 V, +4 mA to +20 mA, and 0 mA to +20 mA.
The circuit is powered from a standard 24 V bus supply and generates an isolated 5 V system supply voltage.
Применяемые компоненты
AD5700-1
Малопотребляющий HART модем с прецизионным внутренним генератором
AD7173-8
Малопотребляющий, 8-/16-канальный, 24-разрядный сигма-дельта АЦП с высокой степенью интеграции, быстродействие 31.25 kSPS
ADG704
CMOS, Low Voltage 2.5 Ω 4-Channel Multiplexer
ADP2441
Синхронный понижающий стабилизатор постоянного напряжения, 36 В/1 А
ADUM3151
3.75 kV, 7-Channel, SPIsolator Digital Isolators for SPI (with 2/1 Aux channel directionality)
ADUM5211
Dual-Channel Isolators with Integrated DC-to-DC Converter (1/1 Channel Directionality)
AD7176-2
24-разрядный сигма-дельта АЦП с быстродействием 250 kSPS и временем установления 20 мкс
AD7173-8
Малопотребляющий, 8-/16-канальный, 24-разрядный сигма-дельта АЦП с высокой степенью интеграции, быстродействие 31.25 kSPS
AD7175-2
24-разрядный сигма-дельта АЦП с Rail-to-Rail буферами, быстродействием 250 kSPS и временем установления 20 мкс
AD7172-2
Малопотребляющий 24-разрядный сигма-дельта АЦП с Rail-to-Rail буферами, быстродействие 31.25 KSPS
AD7177-2
32-разрядный сигма-дельта АЦП с быстродействием 10 kSPS, временем установления 100 мкс и Rail-to-Rail буферами
AD7172-4
Малопотребляющий 4-/8-канальный, 24-разрядный сигма-дельта АЦП с Rail-to-Rail буферами, быстродействие 31.25 kSPS
Области применения
CN0375

The circuit shown in Figure 1 is a broadband low distortion RF transmitter with a dual high speed TxDAC+ digital-to-analog converter (DAC), a wideband I/Q modulator, and an output driver amplifier.
The devices are well matched, and the direct interface between the DAC and the modulator, and between the modulator and the driver amplifier, offers a compact solution for many RF communications applications including 3G, 4G, and LTE.
Применяемые компоненты
Области применения
CN0387

The circuit shown in Figure 1 accurately measures return loss in a wireless transmitter from 1 GHz to 28 GHz without any need for system calibration.
The design is implemented on a single circuit board using a nonreflective RF switch; a microwave RF detector; and a 12-bit, precision analog-to-digital converter (ADC). To evaluate the circuit over the widest possible frequency range, a dual-port directional coupler with SMA connectors was used instead of a narrow-band, surface-mount directional coupler.
The circuit measures return loss of up to 20 dB over an input power range of 25 dB (return losses in excess of 20 dB can be measured over a smaller input power range).
A unique feature of the circuit is that it calculates return loss using a simple ratio of the digitized voltages from the RF detector, thereby eliminating the need for system calibration.

Применяемые компоненты
ADL6010
Детектор мощности с коротким временем отклика, динамический диапазон 45 дБ, диапазон частот 500 МГц - 40 ГГц
AD7091R
Малопотребляющий 12-разрядный АЦП с интегрированным источником опорного напряжения в 10-выводных корпусах LFCSP и MSOP, быстродействие 1 MSPS
HMC547
HMC547LC3 / HMC547LP3
GaAs MMIC, High Isolation SPDT Nonreflective Switch SMT, DC to 28.0 GHz
Области применения
CN0399

The circuit shown in Figure 1 is an RF power measurement circuit that accurately measures the power from an RF signal source within a frequency range of 9 kHz to 6 GHz, and has a nominal input power range of 45 dBm (−30 dBm to +15 dBm).
This circuit constitutes a complete rms RF power meter in a tiny form factor that can be powered entirely from a 5 V USB power supply. The measurement signal chain consists of an rms responding RF power detector and a 12-bit, precision analog-to-digital converter (ADC). These devices are powered by a CMOS linear regulator which generates 3.3 V from the 5 V USB supply.A simple calibration routine can be performed at multiple frequencies to compensate for any frequency response variation of the circuit. Calibration data is stored in a lookup table, which is referenced during the RF power measurement.
Figure 1. Portable RF Power Meter Evaluation Board Measurement Setup (All Connections and Decoupling Not Shown)
Применяемые компоненты
ADP160
Линейный КМОП стабилизатор с крайне низким потребляемым током, выходной ток 150 мА
AD7091R
Малопотребляющий 12-разрядный АЦП с интегрированным источником опорного напряжения в 10-выводных корпусах LFCSP и MSOP, быстродействие 1 MSPS
ADL5904
DC to 6 GHz, 45 dB TruPwr Detector with Envelope Threshold Detection
Области применения
CN0405

This circuit shown in Figure 1 provides a complete solution that replaces a classical high voltage mechanical potentiometer with a push-button controlled digital potentiometer.
The circuit allows a low voltage digital potentiometer to control a high voltage source up to 20 V from batteries or other sources through simple push-button switches, offering ease of use and optimum power efficiency. The AD5116 digital potentiometer provides 64 wiper positions with an end-to-end resistor tolerance error of ±8%, making it suitable for wide range of adjustment.
In addition, the AD5116 contains an EEPROM that can manually save the wiper position to its desirable position through a push-button. This feature is useful in applications requiring a default position on power-up.

Применяемые компоненты
ADP2441
Синхронный понижающий стабилизатор постоянного напряжения, 36 В/1 А
ADP121
Линейный КМОП стабилизатор с низким потребляемым током в 5-выводном корпусе TSOT или корпусе WLCSP с 4 контактами, выходной ток 150 мА
ADCMP371
Универсальный компаратор с двухтактным выходным каскадом
AD5116
Одноканальный цифровой потенциометр на 64 позиции с энергонезависимой памятью и кнопочным управлением с допуском номинального сопротивления ±8%
Области применения
CN0156

The circuit shown in Figure 1 provides a simple approach for controlling the amplitude of the output waveform of an AD9834 75 MHz low power (20 mW) waveform generator (DDS).
DDS (direct digital synthesis) devices are capable of producing sine wave, square wave, and triangular output waveforms and, therefore, serve as waveform generators.
Capability for phase modulation and frequency modulation is provided internally in the AD9834. However, in order to modulate the amplitude of the output signal, a low power DAC or digital potentiometer is required to set the full-scale current. A voltage output DAC can be used to drive the FS ADJUST pin of the AD9834 through a series resistor. This determines the magnitude of the full-scale DAC current.
The DAC used in this example is the 12-bit AD5620, a member of the nanoDAC family. The AD5620 contains an on-chip 5 ppm/°C reference, has an SPI interface, and is available in an 8-lead SOT-23 or MSOP package. The low power (2.2 mW @ 3.3 V) and small size of the AD5620 (8-lead SOT-23) provide an attractive solution for generating an amplitude modulated output from the AD9834.

Применяемые компоненты
Области применения
CN0144

This circuit is a complete implementation of the analog portion of a broadband direct conversion transmitter (analog baseband in, RF out). RF frequencies from 68.75 MHz to 2.2 GHz are supported through the use of a PLL with a broadband integrated voltage controlled oscillator (VCO). Unlike modulators that use a divide-by-1 LO stage (as described in CN-0134), harmonic filtering of the LO is not required.
To achieve optimum performance, the only requirement is that the LO inputs of the modulator be driven differentially. The ADF4350 provides differential RF outputs and is, therefore, an excellent match. This PLL-to-modulator interface is applicable to all I/Q modulators and I/Q demodulators that contain a 2XLO-based phase splitter. Low noise LDOs ensure that the power management scheme has no adverse impact on phase noise and error vector magnitude (EVM). This combination of components represents industry-leading direct conversion transmitter performance over a frequency range of 68.75 MHz to 2.2 GHz. For frequencies above 2.2 GHz, it is recommended to use a divide-by-1 modulator, as described in CN-0134.

Применяемые компоненты
Области применения
CN0249

The circuit shown in Figure 1 is a simplified diagram of a 14-bit, 125 MSPS quad ADC system that uses post digital summation to increase the signal-to-noise ratio (SNR) from 74 dBFS for a single ADC to 78.5 dBFS for the quad ADC with summation. This technique is especially suitable for applications requiring high SNR such as ultrasound and radar, and makes use of modern high performance low power quad pipelined ADCs.
The circuit makes use of the fundamental principle that uncorrelated noise sources add on a root-sum-square (rss) basis, while signal voltages add on a linear basis.

Применяемые компоненты
AD9253
4-канальный, 14-разрядный, 80/105/125 MSPS аналого-цифровой преобразователь с последовательным LVDS интерфейсом и питанием 1,8 В
Области применения
CN0171

The circuit shown in Figure 1 uses the ADL5535/ADL5536 single-ended IF low noise 50 Ω gain block to drive the AD9268 16-bit differential input analog-to-digital converter (ADC). The circuit includes an interstage bandpass filter for noise reduction and anti-aliasing. The use of a single-ended IF gain stage followed by a transformer to perform the single-ended- to-differential conversion is an optimum solution for this application where both low noise and low distortion are required.
The ADL5535/ADL5536 is a high linearity (third order output intercept, OIP3 = +45 dBm at 190 MHz), single-ended, fixed gain amplifier that can be used as a driver for high performance IF sampling of analog-to-digital converters. The ADL5535 has a gain of 16 dB and provides a simple approach to raise the signal from approximately 400 mV p-p to the 2 V p-p full-scale level required by the ADC. The ADL5535 low noise figure (3.2 dB at 190 MHz) and low distortion ensure that the ADC performance is not compromised. The ADL5536 can be used where a gain of 20 dB is required.
Figure 1. Schematic of the ADL5535 Driving the AD9268 16-Bit ADC, (Simplified Schematic: All Connections and Decoupling Not Shown)
Применяемые компоненты
Области применения
CN0186

The standard single channel direct digital synthesizer (DDS) does not switch between frequencies in a phase coherent manner. By design, DDS frequency transitions are phase continuous (see Figure 2, for example). However, the circuit shown in Figure 1 demonstrates how to configure the AD9958/AD9959 multichannel DDS for a robust phase coherent FSK (frequency shift keying) modulator by summing the outputs of the multichannel DDS together.
A multichannel DDS virtually eliminates temperature and timing issues between channels compared to synchronizing multiple single channel devices for the same application. For instance, multichannel DDS outputs, though independent, share the same system clock edges in the chip. Consequently, the system clock edges across multiple chips would not track as well over temperature and power supply deviations compared to an integrated multichannel DDS. As a result, a multichannel DDS is better suited for producing a closer to ideal phase coherent frequency transition at the summed output.

Применяемые компоненты
AD9520-0
Генератор тактовых сигналов с 12 каналами LVPECL/24 каналами КМОП и интегрированным ГУН диапазона 2.8 ГГц
AD9520-1
Генератор тактовых сигналов с 12 каналами LVPECL/24 каналами КМОП и интегрированным ГУН диапазона 2.5 ГГц
AD9520-2
Генератор тактовых сигналов с 12 каналами LVPECL/24 каналами КМОП и интегрированным ГУН диапазона 2.2 ГГц
AD9520-3
Генератор тактовых сигналов с 12 каналами LVPECL/24 каналами КМОП и интегрированным ГУН диапазона 2 ГГц
AD9520-4
Генератор тактовых сигналов с 12 каналами LVPECL/24 каналами КМОП и интегрированным ГУН диапазона 1.6 ГГц
AD9520-5
Генератор тактовых сигналов с 12 каналами LVPECL/24 каналами КМОП
AD9958
Двухканальный синтезатор прямого цифрового синтеза с быстродействием 500 MSPS и 10-разрядными ЦАП
AD9959
Четырехканальный синтезатор прямого цифрового синтеза с быстродействием 500 MSPS и 10-разрядными ЦАП
Области применения
CN0178

This circuit uses the ADL5902 TruPwr™ detector to measure the rms signal strength of RF signals with varying crest factors (peak-to-average ratio) over a dynamic range of approximately 65 dB and operates at frequencies from 50 MHz up to 9 GHz.
The measurement result is provided as serial data at the output of a 12-bit ADC (AD7466). A simple 4-point system calibration at ambient temperature is performed in the digital domain.
The interface between the RF detector and the ADC is straightforward, consisting of two signal scaling resistors and no active components. In addition, the ADL5902 internal 2.3 V reference voltage provides the supply and reference voltage for the micropower ADC. The AD7466 has no pipeline delay and is operated as a read-only SAR ADC.
The overall circuit achieves temperature stability of approximately ±0.5 dB.Data is shown for the two devices operating over a −40°C to +85°C temperature range.

Применяемые компоненты
Области применения
CN0285

This circuit is a complete implementation of the analog portion of a broadband direct conversion transmitter (analog baseband in, RF out). RF frequencies from 500 MHz to 4.4 GHz are supported using a phase-locked loop (PLL) with a broadband, integrated voltage controlled oscillator (VCO). Harmonic filtering of the local oscillator (LO) from the PLL ensures excellent quadrature accuracy, sideband suppression, and low EVM.


Low noise, low dropout regulators (LDOs) ensure that the power management scheme has no adverse impact on phase noise and EVM. This combination of components represents industry leading direct conversion transmitter performance over a frequency range of 500 MHz to 4.4 GHz.
Применяемые компоненты
Области применения
CN0311

This circuit is a complete implementation of the analog portion of a broadband direct conversion transmitter (analog baseband in, RF out). RF frequencies from 30 MHz to 2.2 GHz are supported by using a phase-locked loop (PLL) with a broadband integrated voltage controlled oscillator (VCO). Unlike modulators that use a divide-by-1 local oscillator (LO) stage (as described in CN-0285), harmonic filtering of the LO is not required.
To achieve optimum performance, the only requirement is that the LO inputs of the modulator be driven differentially. The ADF4351 provides differential RF outputs and is, therefore, an excellent match. This PLL-to-modulator interface is applicable to all I/Q modulators and I/Q demodulators that contain a 2XLO-based phase splitter. Low noise LDOs ensure that the power management scheme has no adverse impact on phase noise and error vector magnitude (EVM). This combination of components represents an industry-leading direct conversion transmitter performance over a frequency range of 30 MHz to 2.2 GHz. For frequencies above 2.2 GHz, it is recommended to use a divide-by-1 modulator, as described in CN-0285.

Применяемые компоненты
Области применения
Связь
CN0150

This circuit measures RF power at any frequency from 1 MHz to 8 GHz over a range of approximately 60 dB. The measurement result is provided as a digital code at the output of a 12-bit ADC with serial interface and integrated reference. The output of the RF detector has a glueless interface to the ADC and uses most of the ADC’s input range without further adjustment. A simple two-point system calibration is performed in the digital domain.
The AD8318 maintains accurate log conformance for signals of 1 MHz to 6 GHz and provides useful operation to 8 GHz. The device provides a typical output voltage temperature stability of ±0.5 dB.
The AD7887 ADC can be configured for either dual or single channel operation via the on-chip control register. There is a default single-channel mode that allows the AD7887 to be operated as a read-only ADC, thereby simplifying the control logic.
Typical data is shown for the two devices operating over a −40°C to +85°C temperature range.

Применяемые компоненты
AD8318
Логарифмический детектор/контроллер, диапазон частот 1 МГц - 8 ГГц, динамический диапазон 70 дБ
ADR421
Ultraprecision, Low Noise, 2.500 V XFET® Voltage References
AD7887
Микропотребляющий двухканальный 12-разрядный АЦП в 8-выводном корпусе MSOP, питание 2.7 В - 5.25 В, быстродействие 125 kSPS
Области применения
CN0134

This circuit is a complete implementation of the analog portion of a broadband direct conversion transmitter (analog baseband in, RF out). RF frequencies from 500 MHz to 4.4 GHz are supported through the use of a PLL with a broadband integrated voltage controlled oscillator (VCO). Harmonic filtering of the LO from the PLL ensures excellent quadrature accuracy.
Low noise LDOs ensure that the power management scheme has no adverse impact on phase noise and EVM. This combination of components represents industry-leading direct conversion transmitter performance over a frequency range of 500 MHz to 4.4 GHz.

Применяемые компоненты
Области применения
CN0147

This circuit uses low noise, low dropout (LDO) linear regulators to supply power to a wideband integrated PLL and VCO. Wideband voltage controlled oscillators (VCOs) may have increased sensitivity to power supply noise, hence, ultralow noise regulators are recommended for best performance.
The circuit shown in Figure 1 utilizes the ADF4350, a fully integrated fractional-N PLL and VCO that can generate frequencies from 137.5 MHz to 4400 MHz. The ADF4350 is powered from the ultralow noise 3.3 V ADP150 regulator for optimal LO phase noise performance.

The lower integrated rms noise of the ADP150 LDO of only 9 μV rms (10 Hz to 100 kHz) helps to minimize VCO phase noise and reduce the impact of VCO pushing (the VCO equivalent of power supply rejection).
Figure 2 shows a photo of the evaluation board, which uses the ADP150 LDOs to power the ADF4350. The ADP150 represents the industry’s lowest noise LDO in the smallest package at the lowest cost. It is available in a 4-ball, 0.8 mm × 0.8 mm, 0.4 mm pitch WLCSP or a convenient 5-lead TSOT package. Adding the ADP150’s to the design, therefore, has minimal impact on system cost and board area while providing a significant improvement in phase noise.

Применяемые компоненты
Области применения
CN0325

The circuit shown in Figure 1 provides two, 16-bit, fully isolated, universal analog input channels suitable for programmable logic controllers (PLCs) and distributed control system (DCS) modules. Both channels are software programmable and support a number of voltage, current ranges, thermocouple, and RTD types, as shown in Figure 1.

The evaluation board contains two different fully isolated universal input channels, one with a 4-pin terminal block (CH2), and one with a 6-pin terminal block (CH1).
For the 4-terminal block channel (CH2), the voltage, current, thermocouple, and RTD inputs all share the same 4 terminals, thus minimizing the number of terminal pins required. For the 6-pin terminal block channel (CH1), the voltage and current inputs share a set of 3 terminals, and the thermocouple and RTD inputs share another set of 3 terminals; this configuration requires more terminals but has a lower part count and component cost. Figure 2 shows a photo of the printed circuit board (PCB), and Figure 3 shows a more detailed schematic of the circuit.


Применяемые компоненты
AD7795
Шестиканальный, малопотребляющий 16-разрядный сигма-дельта АЦП с низким шумом, интегрированным ИУ и источником опорного напряжения
ADR441
Ultralow Noise, LDO XFET® 2.5V Voltage Reference w/Current Sink and Source
ADUM1311
Triple-Channel Digital Isolators
ADG442
LC2MOS Quad SPST Switch
AD8226
Инструментальный усилитель с широким диапазоном напряжений питания и Rail-to-Rail выходом
ADT7310
16-разрядный цифровой датчик температуры с интерфейсом SPI, погрешность ±0.5°C
ADP2441
Синхронный понижающий стабилизатор постоянного напряжения, 36 В/1 А
ADUM3471
Isolated Switching Regulators (3/1 Channel Directionality)
ADP1720
Высоковольтный, микропотребляющий линейный стабилизатор, выходной ток 50 мА
Области применения
CN0279

The circuit, shown in Figure 1, is a narrow, band-pass receiver front end based on the ADL5565 ultralow noise differential amplifier driver and the AD9642 14-bit, 250 MSPS analog-to-digital converter (ADC).
The third-order, Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 5.8 dB.
The overall circuit has a bandwidth of 18 MHz with a pass-band flatness of 3 dB. The signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) measured with a 127 MHz analog input are 71.7 dBFS and 92 dBc, respectively. The sampling frequency is 205 MSPS, thereby positioning the IF input signal in the second Nyquist zone between 102.5 MHz and 205 MHz.
Применяемые компоненты
Области применения
CN0294

Many systems require low jitter multiple system clocks for mixed signal processing and timing. The circuit shown in Figure 1 interfaces the ADF4351 integrated phase-locked loop (PLL) and voltage-controlled oscillator (VCO) to the ADCLK948, which provides up to eight differential, low voltage, positive emitter coupled logic (LVPECL) outputs from one differential output of the ADF4351.

Modern digital systems often require many high quality clocks at logic levels that are different from the logic level of the clock source. Extra buffering may be required to guarantee accurate distribution to other circuit components without loss of integrity. The interface between the ADF4351 clock source ADCLK948 clock fanout buffer is described, and measurements show that the additive jitter associated with the clock fanout buffer is 75 fs rms.
Применяемые компоненты
Области применения
CN0243

The combination of the ADRF6702 IQ modulator and the AD9122 16-bit dual 1.2 GSPS TxDAC has the dynamic range necessary for a modern high level QAM or OFDM based wireless transmitter as shown in Figure 1. The dynamic range of this circuit is good enough to enable both ZIF (zero IF/baseband) and CIF (complex IF up to 200 MHz to 300 MHz). The AD9122 has the option of up to 8× interpolation, as well as a 32-bit NCO for very fine IF frequency selectivity.
Overall performance of a transmitter is highly dependent on the dynamic range of the components directly in the signal chain. In a mixed-signal transmitter using a DAC and IQ modulator, the noise floor and distortion characteristics of these components define the overall dynamic range of the signal chain. However, the noise floor of the DAC can also be degraded by sample clock jitter, and the IQ modulator performance is dependent on the noise and spur characteristics of its local oscillator (LO). Using high performance components for sample clock and LO generation is, therefore, key to a high performance transmitter.
In addition, generating these signals physically close to the DAC and modulator on the PCB and using a single external reference can make the design much simpler. Generating the sample clock and LO (LO is very often a multi-GHz signal) separately and at some distance from the DAC and IQ modulator requires great care in the PCB layout. Subtle layout errors can cause coupling to and from these critical signals and degrade overall signal chain performance.
The signal chain performance is also heavily dependent on the DAC/ IQ modulator interface filter. For optimal performance, this passive filter should be designed after careful analysis of the required system specifications.
The ADRF6702 includes an on-board fractional PLL for LO generation so that a low frequency reference (typically less than 100 MHz) is all that is necessary to synthesize the IQ modulator LO. Using the PLL in the AD9516 clock generator allows a single reference to generate both the DAC sample clock and the PLL reference for the ADRF6702.
The circuit in Figure 1 was built using the AD9516-0, but other members of the AD9516 family could be used depending on the desired internal VCO frequency.

Применяемые компоненты
AD9516-3
14-канальный генератор тактовых сигналов с интегрированным ГУН диапазона 2.0 ГГц
AD9516-0
14-канальный генератор тактовых сигналов с интегрированным ГУН диапазона 2.8 ГГц
AD9516-1
14-канальный генератор тактовых сигналов с интегрированным ГУН диапазона 2.5 ГГц
AD9122
Dual, 16-Bit, 1200 MSPS, TxDAC+® Digital-to-Analog Converter
ADRF6702
Квадратурный модулятор диапазона 1200 МГц - 2400 МГц с интегрированными схемой ФАПЧ с дробным коэффициентом деления и ГУН с полосой 1550 МГц - 2150 МГц
AD9516-2
14-канальный генератор тактовых сигналов с интегрированным ГУН диапазона 2.2 ГГц
AD9516-4
14-канальный генератор тактовых сигналов с интегрированным ГУН диапазона 1.6 ГГц
Области применения
CN0227

Схема, изображенная на рис. 1, представляет собой входной интерфейс широкополосного приемника, построенный на основе дифференциального усилителя-драйвера с крайне малым шумом ADL5562 и 16-разрядного аналого-цифрового преобразователя с быстродействием 250 MSPS AD9467.
Антиалайзинговый фильтр (фильтр предотвращения спектральных наложений) третьего порядка с характеристикой Баттерворта оптимизирован, исходя из общих требований к схеме и требований к интерфейсу между усилителем и АЦП. Полные потери, вносимые фильтром и другими компонентами, составляют всего 1,8 дБ.
Схема обладает шириной полосы 152 МГц и неравномерностью в полосе пропускания 1 дБ. Отношение сигнал-шум и свободный от побочных составляющих динамический диапазон составляют 72,6 dBFS (дБ к полной шкале) и 82,2 дБн, соответственно, при частоте аналогового входного сигнала 120 МГц.

Применяемые компоненты
Области применения
CN0205

This circuit provides a simple and flexible interface between the AD9122 dual high speed TxDAC digital-to-analog converter and the ADL5375-05 broadband I/Q modulator. Because the DAC outputs and ADL5375-05 I/Q modulator inputs share a common bias level of 0.5 V, there is no need for any active or passive level shifting circuitry. The dc coupled interface facilitates I/Q modulator local oscillator (LO) leakage compensation by the DAC.
The 1.2 GSPS AD9122 DAC sampling rate and the wide bandwidth of the ADL5375-05 modulator I and Q inputs ensure that both zero-IF (ZIF) or complex-IF (CIF) architectures can be supported. In addition to filtering Nyquist images, the baseband filter provides excellent rejection of both differential-mode and common-mode DAC spurs.
Применяемые компоненты
Области применения
CN0238

The circuit, shown in Figure 1, is a wideband receiver front end based on the ADA4960-1 ultralow noise differential amplifier driver and the AD9434 12-bit, 500 MSPS analog-to-digital converter.
The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network, transformer, and other resistive components is only 1.2 dB.
The overall circuit has a bandwidth of 290 MHz with a pass-band flatness of 1 dB. The SNR and SFDR measured with a 140 MHz analog input are 64.1 dBFS and 70.4 dBc, respectively.

Применяемые компоненты
Области применения
CN0268

The circuit shown in Figure 1 is a 16-bit, 250 MSPS, narrow-band, high IF receiver front end with an optimum interface between the ADL5565 differential amplifier and the AD9467 ADC.
The AD9467 is a buffered input 16-bit, 200 MSPS or 250 MSPS ADC with SNR performance of approximately 75.5 dBFS and SFDR performance between 95 dBFS and 98 dBFS. The ADL5565 differential amplifier is suitable for driving IF sampling ADCs because of its high input bandwidth, low distortion, and high output linearity.
This circuit note describes a systematic procedure for designing the interface circuit and the antialiasing filter that maintains high performance and ensures minimal signal loss. A resonant approach is used to design a maximally flat Butterworth fourth-order band-pass filter with a center frequency of 200 MHz.
Figure 1. Resonant Filter Design for Narrow Band High IF Applications Using the ADL5565 Differential Amplifier and the AD9467 ADC
Применяемые компоненты
Области применения
CN0259

The circuit, shown in Figure 1, is a 65 MHz bandwidth receiver front end based on the ADL5565 ultrahigh dynamic range differential amplifier driver and the 11-bit, 200 MSPS AD6657A quad IF receiver.
The fourth-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and IF receiver. The total insertion loss due the filter network and other resistive components is only 2.0 dB. The overall circuit has a bandwidth of 65 MHz, with the low-pass filter having a 1 dB bandwidth of 190 MHz and a 3 dB bandwidth of 210 MHz. The pass-band flatness is 1dB.
The circuit is optimized to process a 65 MHz bandwidth IF signal centered at 140 MHz with a sampling rate of 184.32 MSPS. The SNR and SFDR measured with a 140 MHz analog input across the 65 MHz band are 70.1 dBFS and 80.9 dBc, respectively.

Применяемые компоненты
Области применения
CN0360

This circuit is a frequency selective, radio frequency (RF) detector that offers 90 dB of detection range from 35 MHz to 4.4 GHz. Unlike a standalone detector that does not discriminate between signals in the frequency spectrum, this circuit has the ability to focus on a narrow band of frequencies, providing enhanced performance over the specified range. The detector circuit is rms responding and stable vs. temperature and frequency, making it an attractive solution for applications that require precise frequency, selective RF power measurement. The circuit also demonstrates strong immunity to unwanted blockers. Figure 1 shows a simplified schematic of the circuit.
Figure 1. Frequency Selective RF Detector (Simplified Schematic; All Connections and Decoupling Not Shown)
Применяемые компоненты
Области применения
CN0366

The circuit shown in Figure 1 is an accurate 40 GHz, microwave power meter with a 45 dB range that requires only two components. The RF detector has an innovative detector cell using Schottky diodes followed by an analog linearization circuit. A low power, 12-bit, 1 MSPS analog-to-digital converter (ADC) provides a digital output on a serial peripheral interface (SPI) port.
A simple calibration routine is run before measurement operation, at the particular RF frequency of interest. The user can then operate the system in measurement mode. When in measurement mode, the CN-0366 Evaluation Software displays the calibrated RF input power that is applied at the input of the detector in units of dBm.
The total power dissipation of this circuit is less than 9 mW on a single 5 V supply.
Figure 1. Microwave Power Meter Simplified Schematic (All Connections and Decoupling Not Shown)
Применяемые компоненты
Области применения
CN0369

The circuit block diagram shown in Figure 1 is a low phase noise translation loop synthesizer (also known as an offset loop). This circuit translates the lower 100 MHz reference frequency of the ADF4002 phase locked loop (PLL) up to a higher frequency range of 5.0 GHz to 5.4 GHz, as determined by the frequency of the local oscillator (LO).

The translation loop synthesizer has very low phase noise (<50 fs) in contrast to a synthesizer using only a PLL. The low phase noise is because of the very low N value used by the ADF4002 integer-N PLL, which controls the voltage controlled oscillator (VCO). In this example, the ADF4002 phase frequency detector (PFD) runs at 100 MHz, and N = 1, yielding phase noise performance that is not limited by the N value of the PLL.
Применяемые компоненты
ADL5801
Активный смеситель диапазона 10 МГц – 6 ГГц с высоким IP3
HMC512
VCO with Fo/2 & Divide-by-4 SMT, 9.6 - 10.8 GHz
ADF4355-2
Широкополосный синтезатор диапазона СВЧ с интегрированным ГУН
AD8065
Высокопроизводительный ОУ FastFET™ с шириной полосы 145 МГц
ADP151
Линейный КМОП стабилизатор с крайне низким шумом, выходной ток 200 мА
ADM7150
LDO-стабилизатор с крайне низким шумом и высоким ослаблением пульсаций питания, выходной ток мA
ADF4002
Фазовый детектор/Синтезатор частот с ФАПЧ
Области применения
CN0376

The circuit shown in Figure 1 provides a dual-channel, channel-to-channel isolated, thermocouple or RTD input suitable for programmable logic controllers (PLC) and distributed control systems (DCS). The highly integrated design utilizes a low power, 24-bit, Σ-Δ analog-to-digital converter (ADC) with a rich analog and digital feature set that requires no additional signal conditioning ICs.
Each channel can accept either a thermocouple or a RTD input. The entire circuit is powered from a standard 24 V bus supply. Each channel measures only 27 mm × 50 mm.

Применяемые компоненты
AD7124-4
Четырехканальный 24-разрядный сигма-дельта АЦП с низким шумом, малым энергопотреблением, интегрированными усилителем и источником опорного напряжения
AD7124-8
Восьмиканальный, малопотребляющий 24-разрядный сигма-дельта АЦП с низким шумом, программируемым усилителем и источником опорного напряжения
ADUM5010
2.5kV rms Isolated DC/DC Converter
ADUM1441
Микропотребляющий четырехканальный цифровой изолятор, высокий логический уровень по умолчанию (конфигурация каналов 3/1)
ADP2441
Синхронный понижающий стабилизатор постоянного напряжения, 36 В/1 А
Области применения
CN0374

The circuit shown in Figure 1 precisely converts a 400 MHz to 6 GHz RF input signal to its corresponding digital magnitude and digital phase. The signal chain achieves 0° to 360° of phase measurement with 1° of accuracy at 900 MHz. The circuit uses a high performance quadrature demodulator, a dual differential amplifier, and a dual differential 16-bit, 1 MSPS successive approximation analog-to-digital converter (SAR ADC).

Применяемые компоненты
AD7903
Двухканальный 16-разрядный АЦП PulSAR с дифференциальным входом в корпусе QSOP, быстродействие 1 MSPS, потребляемая мощность 12.0 мВт
ADA4940-2
Драйвер АЦП с крайне низким энергопотреблением и малыми искажениями
ADL5380
Квадратурный демодулятор диапазона 400 - 6000 МГц
ADR435
Ultralow Noise XFET® Voltage References with Current Sink and Source Capability
Области применения
Связь
CN0283

Whether an IQ modulator is used in a direct conversion application or as an upconverter to a first intermediate frequency (IF), some gain is generally applied directly after the IQ modulator. How to choose an appropriate driver amplifier to provide the first stage of gain at the output of an IQ modulator will be described. The devices shown in Figure 1 are the ADL5375 IQ modulator and the ADL5320 driver amplifier. They are well matched from a system performance level; that is, they have equivalent performance so neither device contributes to degradation in the overall performance. Because these devices are well matched in terms of their dynamic ranges, a simple direct connection between the IQ modulator and the RF driver amplifier is recommended without any need for attenuation between the devices.

Применяемые компоненты
Области применения
Связь
CN0304

The circuit shown in Figure 1 is a 75 MHz low power (25 mW total) direct digital synthesis (DDS) waveform generator. The output buffer and anti-imaging filter provide improved spectral performance, making it suitable for frequency generation or clocking applications requiring sine wave, triangular wave, and square outputs up to 18 MHz.
Because they are sampled data devices, low power DDS devices must be followed by a suitable anti-imaging filter to remove spectral images. However, the maximum current output is approximately 4 mA into a recommended 200 Ω load; therefore, an optimum low power, low distortion op amp buffer at the DDS output provides a low impedance drive source for a high quality 50 Ω filter.
The combination of the DDS, output buffer, and seventh-order elliptic low pass filter provides high quality spectral performance.

Применяемые компоненты
Области применения
CN0340


The circuit in Figure 1 is a true rms responding power detector using a variable gain amplifier (VGA) and an rms-responding power detector to provide an extremely wide detection range of approximately 95 dB. RMS detectors are useful in many applications such as receivers and transmitters where accurate measurement of signal power is required. Because the circuit measures rms power, it is suitable for use in systems with diverse or varying crest factors. Examples of such systems include GSM/EDGE, CDMA, WCDMA, TD-SCDMA and LTE based wireless base stations along with any system that uses QAM modulation.
The detection range of the ADL5902 rms detector is 65 dB and is extended to 95 dB by the addition of the linear-in-dB AD8368 VGA. The ADL5902 TADJ function is used to provide temperature stability for the complete circuit. A SAW filter is placed between the VGA to reduce noise and increase sensitivity. This also reduces the frequency range of the circuit to the pass-band range of the SAW filter.
Применяемые компоненты
Области применения
CN0320

This circuit is a flexible, frequency agile, direct conversion IF-to-baseband receiver. A fixed conversion gain of 5 dB reduces the cascaded noise figure. Variable baseband gain is used to adjust the signal level. The baseband ADC driver also includes a programmable low-pass filter that eliminates out-of-channel blockers and noise.
The bandwidth of this filter can be dynamically adjusted as the bandwidth of the input signal changes. This ensures that the available dynamic range of the ADC that this circuit drives is fully used.
The core of the circuit is an integrated IQ demodulator with fractional-N PLL and VCO. With just one (variable) reference frequency, the PLL/VCO can provide and a local oscillator (LO) between 750 MHz and 1150 MHz. Precise quadrature balance and low output dc offsets ensure that there is minimal degradation of the error vector magnitude (EVM).
The interfaces between all of the components in this circuit are fully differential. Where dc coupling is required between stages, the bias levels of the adjacent stages are compatible with each other.
Figure 1. Direct Conversion receiver Simplified Schematic (All Connections and Decoupling Not Shown)
Применяемые компоненты
Области применения
CN0302

The PLL circuit shown in Figure 1 uses a 13 GHz Fractional-N synthesizer, wideband active loop filter and VCO, and has a phase settling time of less than 5 μs to within 5° for a 200 MHz frequency jump.
The performance is achieved using an active loop filter with 2.4 MHz bandwidth. This wide bandwidth loop filter is achievable because of the ADF4159 phase-frequency detector (PFD) maximum frequency of 110 MHz; and the AD8065 op amp high gain-bandwidth product of 145 MHz.
The AD8065 op amp used in the active filter can operate on a 24 V supply voltage that allows control of most wideband VCOs having tuning voltages from 0 V to 18 V.

Применяемые компоненты
Области применения
Актуальные ресурсы по теме
Все ресурсы
Технические статьи
- Reliable PCB Assembly of Land Grid Array Packages in Planar Phased Array Antennas
- How to Model Statistical Tolerance Analysis for Complex Circuits Using LTspice
-
Optimizing Power Systems for the Signal Chain—Part 3: RF Transceivers
Analog Dialogue
-
Optimizing Power Systems for the Signal Chain—Part 2: High Speed Data Converters
Analog Dialogue
-
Optimizing Power Systems for the Signal Chain—Part 1: How Much Power Supply Noise Is Tolerable?
Analog Dialogue
Вебкасты
- X Band Hybrid Beamforming Phased Array Radar System Platform
- RF Front End Design for the ADRV9002 Narrow/Wideband Transceiver
- MEMS IMUs in Autonomous Vehicle Navigation
- Simulated Phased Array Beam Stabilization Demo using ADIS16480 & MATLAB Phased Array System Toolbox Webinar
- Fastest Ever – Innovate with 2.5 Gigabit Digital Isolators
Статьи по применению
- AN-747: Timing Synchronization for Multiple AD9786 TxDACs (Rev. 0) PDF
- AN-0983: Introduction to Zero-Delay Clock Timing Techniques PDF
- AN-1067: The Power Spectral Density of Phase Noise and Jitter: Theory, Data Analysis, and Experimental Results (Rev. 0) PDF
- AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0) PDF
- AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0) PDF
Брошюры и бюллетени
Инструменты проектирования
- AD9208 Delphi Model ZIP
- ADIsimPLL™
- Visual Analog
- ADIsimRF
- Программное обеспечение ADIsimCLK для проектирования и оценки
Видео
Обучающие материалы
- MT-075: Differential Drivers for High Speed ADCs Overview PDF
- MT-019: DAC Interface Fundamentals (Rev. A) PDF
- MT-013: Evaluating High Speed DAC Performance PDF
- MT-012: Intermodulation Distortion Considerations for ADCs PDF
- MT-230: Noise Considerations in High Speed Converter Signal Chains PDF
Информация
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