Get a 3dB SNR Boost Using a Dual ADC

Using a dual channel simultaneous sampling ADC and some simple averaging techniques, the SNR of the converter can be improved by 3dB.

Step 1. Collect data using both channels of the ADC using symmetrical input networks as shown below in Figure 1.

Get a 3dB SNR Boost Using a Dual ADC
Figure 1. LTC6409 Driving Dual Channel LTC2185

This example uses the LTC2185 ADC and the LTC6409 amplifier. There is a single-ended 10MHz low pass filter (LPF) before the amplifier and a simple LPF after the amplifier.  R1 and R2 are driven by the same signal source.

Step 2. Collect the data in an FPGA. Since a dual ADC like the LTC2185 is simultaneously sampling, the two channels will align in the digital domain and they can easily be manipulated.

Step 3. Sum the two channels in the digital domain. Because these signals are simultaneously sampled the data can be summed point for point in the digital domain. 

Here is an example:

Get a 3dB SNR Boost Using a Dual ADC
Table 1. Data From Dual Channel ADC

Once these data points are summed they can then be subject to the remaining digital signal processing of the application. The result will be a 3dB improvement in SNR.


FFT data from both channels individually:

Get a 3dB SNR Boost Using a Dual ADC
Figure 2. FFT Data From Both Channels Individually

FFT data after summation:

Get a 3dB SNR Boost Using a Dual ADC
Figure 3. FFT Data After Summation

Why this works?

This technique is possible because when coherent signals (signals with the same phase, frequency and amplitude characteristics) are summed they sum in terms of voltage. But random signals like noise which are phase-, frequency- and amplitude-independent only sum in terms of power. So the signal of interest will increase by 6dB after summation, and the noise will only increase by 3dB after summation. This will give a net increase in SNR of 3dB. In reality there will be some shared jitter between the two channels that will be coherent, so the actual SNR gain is slightly less than 3dB.


Clarence Mayott


LTC2246Hのデモ・ボードであるDC1151を始め、リニアテクノロジーのほぼ全ての高速ADCデモ・ボードの設計に携わってきました。これらのボードは、評価用ボードとして様々なアプリケーションで用いられています。Clarenceの設計したデモ・ボードは、アンプとADCを合わせたフル・シグナル・チェーンを有しているため、最終カスタマはシステム評価を容易に行うことができます。また、クロックや信号源のボードなどの付随ボードの設計経験も、高速ADCデモ・ボードの評価を容易にするのに役立っています。Clarenceは、様々なパイプラインやSAR ADCに使用するソフトウェアであるPScopeに関し、現在継続中の開発を統率しています。