The Unseen Ring: Taming Parasitics in Buck Converters Using a Snubber

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要約

With increasing demands on power supplies to have a smaller footprint, higher efficiency, and better thermal performance, addressing noise can often be left until late in the design cycle, making it difficult to resolve. While early measures like using Silent Switcher^® regulators or optimizing board layout can help, a more basic circuit—the snubber—can effectively mitigate noise if these initial steps were not taken.

Taking a synchronous buck regulator as an example, this article introduces the problems associated with switching ringing. It then explains how to design and optimize a snubber circuit to dampen this ringing. Using LTspice^® and typical parasitic models, we will simulate the ringing seen on a standard PCB and demonstrate the impact of the calculated snubber values on both the ringing and the overall efficiency.

Background

Modern DC-to-DC converters are continually pushed toward higher efficiency and smaller solution sizes, often achieved by using higher switching frequencies. While this allows for smaller inductors and capacitors, it also increases the impact of parasitics (unintended inductance and capacitance from components and PCB traces). At higher switching speeds, the interaction with these parasitics can cause significant voltage overshoot and ringing at the switching (SW) node.

This ringing not only places additional voltage stress on the FETs but also generates unwanted electromagnetic interference (EMI). EMI is an electromagnetic signal that disrupts the performance of a system through electromagnetic induction, electrostatic coupling, or conduction. It’s a critical design challenge in industries like automotive, medical, and test and measurement, where meeting strict EMI standards is crucial for product certification and time to market.

Understanding Parasitics

The voltage overshoot and ringing at the SW node of a buck converter are a direct result of the fast-switching speed interacting with the parasitic inductances and capacitances within the circuit. These parasitics are formed by the PCB traces and the components themselves, particularly the FETs.

Essentially, the stray inductance from the PCB traces and the FET package forms an LC tank circuit with the FET’s parasitic output capacitance (C_OSS). This makes both the layout and the selection of the MOSFET critical design factors.

While the magnitude of stray inductance varies by design, a value of 5 nH around the power stage FETs is a reasonable starting point for our example simulations. This value can be significantly higher with poor layout, as inductance values can reach up to 10 nH for every 25 mm (1 inch) of trace length.

Figure 1 shows a typical power controller circuit using the LTC3854 with the expected parasitics shown in red.

Snubber Design: Theory and Calculation

What Is a Snubber and How Does It Work?

After understanding the noise generated by switching activity and the parasitic elements causing it, a method to dampen this excess energy can be introduced. A snubber circuit, typically a series resistor-capacitor (RC) network, is used to absorb the voltage spikes and ringing that occur at the SW node.

The snubber works by providing a controlled path for the high frequency energy from the parasitic LC tank. When the switch turns off, the snubber capacitor begins to charge, absorbing the energy that would otherwise cause ringing. The snubber resistor then dissipates this stored energy as heat, effectively damping the oscillations. By introducing a new resonant frequency and adding resistance to the circuit, the snubber reduces the peak voltage and duration of the ringing, protecting the power switches from overvoltage stress.

Figure 2 shows an image of a typical buck converter with the snubber circuit positioned from the SW node to ground as close as possible to the MOSFET.

Snubber Calculation Steps

1. As shown in the measurement technique section, first measure the ringing frequency of the SW node (this will be the peak of the first spike to the peak of the second spike). Reminder: while this discussion lies within simulations, for board-based measurements, bandwidth limiting must be turned off, and a short scope ground must be used to ensure the ringing is visible. A short description of the required measurement technique is included later in the article for reference.
2. Add a capacitance from SW to GND such that it reduces the ringing frequency (fr) by approximately half the measured value above. Experiment with some different capacitance values here.
3. This will give the parasitic capacitance (CP) by dividing that added capacitance by 3.
4. Knowing the parasitic capacitance, the parasitic inductance (L_P) can be calculated by:

   

   The characteristic impedance is calculated by:

   

   To attenuate the ringing, it will be necessary to use a snubber resistor that is approximately equal to the impedance calculated in Equation 2—generally a few ohms.

   

   The capacitance value should then be selected by taking the C_P value calculated in Equation 3 and increasing it by a factor of 1 to 4 times higher.

Simulation and Analysis in LTspice

Having established the foundational knowledge of noise generation, measurement, and initial snubber value calculation, the next step is to simulate these effects. This section utilizes LTspice to demonstrate the impact of PCB parasitics on the SW node ringing and overshoot, as well as the effectiveness of a snubber circuit.

The following analysis will be conducted to compare the buck converter’s operation with and without a snubber.

1. Modeling Parasitics: First, build a model that includes the parasitic elements to show the ringing and overshoot at the SW node without any snubber.
2. Initial Snubber Impact: The circuit will then be simulated with the initially calculated snubber values to demonstrate the reduction in ringing.
3. Snubber Optimization: Then iterate on the snubber component values to find an optimal balance between damping the ringing and minimizing power loss.
4. Efficiency Analysis: Finally, compare the overall efficiency of the buck converter both with and without the optimized snubber to quantify its impact.

Modeling Parasitics and Measuring Ringing

The LTC3854 synchronous buck controller provides an excellent example for demonstrating how a poor layout can introduce significant parasitics, leading to SW node ringing. This device uses external FETs, which makes the layout’s impact especially pronounced. For this simulation, model the effect of a poor layout by including a 5 nH parasitic inductance, a value that’s reasonable given that every 25 mm of PCB trace can add 10 nH or more.

Before calculating the snubber values, it’s essential to understand the extent of this problem. This is typically done by monitoring the SW node with an oscilloscope. To capture the rising voltage waveform accurately, configure the scope’s volts per division to accommodate the full voltage range (0 V to V_IN) and adjust the time base to view a single transition.

Crucially, proper probing technique is essential for an accurate measurement. A common mistake is using the long ground lead of the scope probe, which introduces its own parasitic inductance. This inductance can cause artificial ringing on the measurement, giving a misleading representation of the actual switching activity. It’s critical to replace the long lead with a short ground spring to significantly reduce loop inductance and improve measurement fidelity.

While a detailed explanation of proper hardware measurement techniques is beyond the scope of this article, which focuses on theory and simulation, it’s a critical topic that warrants its own discussion. The images in Figure 3 illustrate the dramatic difference in measurement results, demonstrating how a long ground lead can artificially introduce significant overshoot and ringing, leading to a misdiagnosis of the circuit’s performance.

Unsnubbed Simulation Results

Figure 4 shows the different parasitic inductances and capacitances modelled in the buck converter circuit. Figure 5 then illustrates the impact of these parasitics on the switching (SW) node profile. The LC tank formed by these elements causes significant overshoot and ringing.

As the simulation shows, the voltage peaks at just over 18 V, which is significantly higher than the expected 12 V. This overshoot is a major concern, as it can exceed the absolute maximum voltage ratings of the MOSFET, potentially damaging the component or reducing its long-term reliability. The ringing is also problematic, as it indicates the MOSFET is not operating in its clearly defined on/off states.

Figure 6 shows that the overall efficiency of the circuit is 96.3%, which seems high at first glance. However, note that this efficiency is without a snubber. The following sections will demonstrate how adding a snubber, while crucial for mitigating ringing, will have a small, quantifiable impact on this efficiency.

Parasitic Model and Snubber Not Calculated

Figure 7 shows the same schematic as Figure 4, but with a simple RC snubber included from the SW node to ground. Note that this is a guessed starting snubber value and has not yet been calculated, so it will not be optimal.

Figures 8 shows the resulting SW node waveform, which has been significantly improved. The peak overshoot is approximately 4 V lower at 14 V, and the oscillation seen after turn-on has been significantly reduced. However, the efficiency has been reduced significantly to 58.9% (see Figure 9), with the majority of the loss associated with the snubber resistor. This demonstrates that while an unoptimized snubber can mitigate ringing, it can also drastically reduce efficiency.

Optimizing the Snubber

Now, let’s optimize the snubber values by following the calculations set out earlier in this document. The goal is to select an RC snubber that effectively dampens the ringing without causing excessive power loss.

First, determine the parasitic LC components of the circuit. The initial simulation (without a snubber) showed a ringing frequency of 23.41 MHz.

Then, add a known capacitor from the SW node to ground to observe the change in the ringing frequency. A new simulation with a 14,000 pF capacitor at the SW node reduces the ringing frequency to 12 MHz. Using the resonant frequency formula fo = 1/(2 × PI√LC ) can determine the parasitic capacitance. The change in frequency is caused by the increase in total capacitance. The new total capacitance (C_total) is:

C_total = C_parasitic + C_added

The relationship between the original frequency (fold) and the new frequency (f_new) is:

Solving for C_parasitic:

This indicates that the circuit has a parasitic capacitance of approximately 5,000 pF. With the parasitic capacitance, the parasitic inductance can be calculated:

The impedance of the circuit is calculated by:

The snubber resistance is set to be greater than the characteristic impedance noted above, in this case, a standard value of 1.5 Ω.

Next, the snubber capacitance, C_snubber, is typically sized to be at least equal to the parasitic capacitance, up to four times this value. For this initial simulation, use a value that is double the parasitic capacitance to ensure sufficient energy absorption, setting C_snubber = 2 × C_parasitic = 2 × 5,000 pF = 10,000 pF.

With the optimized snubber resistance and capacitance, plug these values back into the LTspice simulation to see how the circuit performs.

Figure 10 shows the resulting waveform with a 1.5 Ω + 10,000 pF snubber network. The ringing has been significantly dampened, as intended by the optimized design. The overshoot has also been reduced from over 18 V to 17.2 V with these calculated snubber values. While some overshoot remains, this result highlights the inherent trade-off in snubber design: perfectly eliminating all overshoot and ringing often requires snubber values that result in greater power loss and reduced efficiency.

Furthermore, the overall efficiency is now 94.8% (see Figure 11), which is a significant improvement over the 58.9% seen with the uncalculated snubber. There will always be some efficiency impact with a snubber, as the resistor dissipates a small amount of power. However, by optimizing the component values based on the parasitic LC tank, the impact on efficiency can be minimized.

Conclusion

Understanding and mitigating switching node ringing is a critical step in designing a reliable switching regulator. As shown, this high frequency noise is not an inherent flaw, but a direct consequence of the parasitic LC tank formed by PCB trace inductance and the switching components’ capacitance.

By taking a methodical approach—by accurately simulating the undamped ringing frequency and associated voltage overshoot—the problem can be demystified. This allows for calculating a precise snubber network value, where the resistor critically damps the circuit by matching the parasitic impedance, and the capacitor acts as an energy sink.

The simulation examples clearly demonstrate that a well-designed snubber is an elegant and effective solution. It trades a small, manageable power loss for a significant improvement in both EMI performance and system reliability. Ultimately, incorporating this simple but powerful RC network can quickly transform a noisy and potentially vulnerable power supply into a clean and dependable one, ensuring the longevity and compliance of the final product.

Reference

Ballar, Wesley and Jacob Ciolfi. "Lab Skills for Switch-Mode Power Supply Evaluation—Part 1" Analog Dialogue, Vol. 59, January 2025.

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