要約
Stepdown buck regulators are extremely popular in a variety of portable and nonportable equipment. These buck converters are terminated with an input capacitor, C_{IN} and an output capacitor, C_{O}, at the output. C_{IN} provides highfrequency filtering, so that V_{IN} has low ripple. This application note helps a system designer to setup Mathcad and compute C_{IN} for a particular stepdown DCDC regulator design.
Stepdown buck regulators are used in portable and nonportable equipment, such as PDAs, cell phones, computers, telcom/networks, and consumer products. These buck converters are terminated with an input capacitor, C_{IN}, at the input, and an output capacitor, C_{O}, at the output. The function of both capacitors is to provide highfrequency filtering, so that V_{IN} and V_{O} are close to pure DC, with little ripple noise.
A capacitor is often represented by a series combination of R, L, and C. R is the equivalent series resistance (ESR) and L is the equivalent series inductance (ESL). The term C is equal to the ideal capacitor value.
Figure 1 shows a typical schematic of a synchronous buck power stage and the associated waveforms to be used for the derivations and calculations.
Setting up variables and data for example calculation in MathCad:
Input Voltage  V_{I} := 12  n := 10^{9} 
Output Voltage  V_{O} := 3.3  u := 10^{6}, k := 10³ 
Output Current  I_{O} := 25  m := 10^{3} 
HighSide Switch Drop  V_{HS} := 0.227  
LowSide Switch Drop  V_{LS} := 0.113  
Switching Current Rise Time  T_{RS} := 25 × n  
Switching Current Fall Time  T_{FS} := 25 × n  
Switching Frequency  F_{S} := 600 × k  
Duty Cycle  D := (V_{O} + V_{LS}) / (V_{I}  V_{HS} + V_{LS})  D = 0.287 
Switch(Q1) On Time  T_{ON} := D / F_{S}  
Switch(Q1) Off Time  T_{OFF} := 1 / F_{S}  T_{ON}  
Converter Efficiency  η := 0.9  
Input Current  I_{IN} := V_{O} × I_{O} / η × V_{I}  I_{IN} := 7.639 
Output Inductor PkPk Ripple Current  I_{RPL} := 0.3 × I_{O} 

Input Capacitor  C_{IN} := 40 × u  (4 x 10uF ceramic of ESR = 10mΩ each and ESL = 2.5nH each) 
Input Capacitor ESR  ESR_{CIN} := 2.5 × m  
Input Capacitor ESL  ESL_{CIN} := 0.625 × n 
As seen in Figure 1, the output ripple current through the input capacitor results in voltage across C_{IN} that reflects the values of ESR, ESL, and C. The ESR and ESL cause fast step voltage rise and fall, whereas C has a linear voltage rise and fall due to the fact that the capacitor charges and discharges. At the start of T_{ON}, C_{IN} sees a negative step current, which will produce a negative step voltage given by the following equation:
During T_{ON}, the capacitor discharges an average current of (I_{O}I_{IN}), which causes a linear ΔV of:
The total voltage deviation from the start of T_{ON} to the end of T_{ON} is the summation of the above:
Similarly, but with opposite polarity, at the start of T_{OFF} and during T_{OFF}, the following voltage deviations are calculated:
The peaktopeak ripple is equal to the higher of the two, which is ΔVOFF~1V. As seen from the above, most of the ripple is caused by ESL and the fast di/dt. Di/dt of 1A/nS is very realistic in today's MHz DCDC converters. Therefore, to reduce the ripple, more capacitors would need to be placed in parallel. Lower value ceramic capacitors, such as 0.1uF in the 0805 or 1206 package, have half the ESL of the 10uF, or ~1.2nH. Place the 0.1uF as close as possible to the sensitive decoupling points.
Another parameter that needs to be determined is the RMS current through the input capacitor, so that the capacitor I_{RMS} rating is not exceeded. From the I_{CIN} waveform, the RMS current can be approximated (since the peaktopeak inductor ripple current is usually 2030% of I_{O} max) to be:
Where D = (V_{O} + V_{LS}) / (V_{IN} + V_{LS} + V_{HS}), and I_{IN} = (V_{O} × I_{O}) / η × V_{IN}
To simplify further, let D = V_{O}/V_{IN} (since V_{0} >> V_{LS}, and V_{IN} + V_{LS}  V_{HS} ~ V_{IN}), and I_{IN} = V_{O} × I_{O}/V_{IN} (since efficiency η ~ 1), so that the I_{CINRMS} equation above becomes:
The simplified version produces only ~1.4% error, and involves only three known parameters: V_{I}, V_{O}, and I_{O}. V_{O} is fixed, and I_{O}, V_{I} can have a specified range, depending on the application. However, I_{CINRMS} always has a maximum value of I_{O}/2, which happens at V_{I} = 2V_{O}, and decreases the value for V_{I} < 2I_{O} and V_{I} > 2L_{O}. The plot in Figure 2 below illustrates this:
Due to the high di/dt and pulsating current, a ceramic capacitor is chosen, for its low ESR and ESL. A higher ripple current rating is required at highfrequency to contain the switching spikes. Make sure the RMS current rating of the capacitor is well above the maximum operating RMS current. For longterm reliability, choose a capacitor that will exhibit less than a 10°C temperature rise. Most capacitor manufacturers provide plots that show RMS current vs. temperature rise.