14-Bit Monolithic ADCs: First to Sample Faster than 1 MSPS

1.25 to 10 MSPS pin-compatible AD924xs enable new applications in communications and imaging

The AD924x family are the industry's first monolithic 14-bit analog-to-digital converters (ADCs) to exceed a 1-MHz sample rate. The three pin-compatible devices in MQFP-44 packages, AD9240, AD9243, and AD9241 are specified at 10, 3, and 1.25-MHz clock rates, respectively. With their 12-bit counterparts, the AD9220/23/21 family, they form a complete set of high-performance CMOS A/D converter solutions.

The monolithic single-supply AD924x series of converters at last offer the benefits of high performance, accompanied by significant savings of cost, power, and board space. The assembled hybrids and modules that they will supplant cost many hundreds of dollars, dissipate watts of power, and are typically packaged in large 24- pin DIPs; they operate from a minimum of two supplies and are usually specified for the 0 to 70°C commercial temperature range. The AD924x family is 5 to 20 times less costly in price and power than a popular family of competitive hybrids, are smaller, and have better dynamic specifications. The table lists some of the key specifications of the AD924x family [SNR (signal-to-noise ratio), SINAD (signal to noise & distortion), THD (total harmonic distortion) and SFDR (spurious-free dynamic range)]. The devices operate from a single 5-V supply and have the low power dissipation shown.

AD9240 AD9243 AD9241
Update rate (MSPS)
10 3 1.25
AIN frequency (kHz) 500 500
SNR (dB typ/min) 78.5/76 80/77 79/75.5
SINAD (dB typ/min) 77.5/75 79/76 78/74.5
THD (dB typ/max) -85/-77
-87/-80 -88/-77.5
SFDR (dB typ) 90 91 88
Power dissipation (W max) 0.33 0.145 0.085

Their high performance, low power, and low price are of particular relevance in emerging and next-generation consumer applications, such as communications and imaging. They will be used in cellular and PCS basestations, ADSL/HDSL modems, flatbed and drum document scanners, film and x-ray scanners, infra-red and medical imagers.

For communications, wide input bandwidth, low distortion & wide dynamic range, and low power are major attractions. Wide dynamic range helps to reduce gain requirements in the receiver IF strip. High input bandwidth allows the AD924x family to be used in undersampling applications to perform IF to baseband down-conversion/ mix-down. For imaging, their low noise, 14-bit no-missing code, and SNR performance are key. In addition, infra-red imaging applications benefit from low power dissipation (heat generation); the ADC can reside closer to the IR sensor.Yet other applications for high performance, low power, and low price include: instrumentation, radar, collision-avoidance systems, test equipment, signal analysis, and data acquisition.

Like many high speed converters offered by Analog Devices, the AD924x series is based on a multibit, pipelined architecture, but it is implemented in low-power switched-capacitor circuitry. Figure 1 shows a block diagram of the complete ADC. A low-noise, wideband sample-hold amplifier (SHA) with differential outputs precedes the pipelined core, and accepts single-ended or differential inputs up to 5 V p-p. From the SHA's output, the signal path is fully differential. The first pipeline stage converts the 5 most significant bits and amplifies the remainder, or residue, for successive conversions by the next three 4-bit stages. The results of these partial conversions by the four pipeline stages are then time-aligned and added (with one bit of overlap) to obtain the final 14-bit result. Each clock cycle produces a new conversion, with 3-cycle latency.

Figure 1
Figure 1. 14-bit pipelined ADC architecture.

The converter's overall DC accuracy (INL, DNL) largely depends on the accuracy of the first pipeline stage, which is limited by capacitor mismatch. By converting 5 bits in the first pipeline stage, the effects of capacitor mismatch are sufficiently suppressed to achieve 14-bit accuracy without the need for on-chip calibration. Integral and differential nonlinearity are typically ±2.5 and ±0.6 LSB, respectively.

The dynamic and noise performance of the A/D are largely determined by performance of the input SHA, which was carefully optimized to provide low noise and distortion over a moderately wide bandwidth. Typical input-referred noise is 0.36 LSB, or 110 mV rms. Figure 2 compares typical S/(N+D) and total harmonic distortion (THD) as a function of input frequency for the three devices at their specified sampling rates. These plots demonstrate superior dynamic performance well beyond the devices' respective Nyquist frequencies.

Figure 2
Figure 2. SINAD and THD vs. Signal Frequency

The on-chip bandgap voltage reference can be pin-strapped to 1 V or 2.5 V, or set for any voltage in between using an external resistor divider. Optionally, an external voltage reference may be used. The AD924x family, packaged in a 44-pin MQFP, operates over the -40 to +85°C extended industrial temperature range.


Mike Walsh

Larry Singer

Larry Singer

Larry Singerは、アナログ・デバイセズのディビジョン・フェローです。1987年からマサチューセッツ州ウィルミントンを拠点とし、高速、高分解能のADC/DACを多数設計してきました。それらの中には、BiCMOS/CMOSプロセスで製造されるサブレンジング型、パイプライン型、インターリーブ型のアーキテクチャを採用した製品が含まれます。現在は、インターリーブ型のADC、パイプライン型のADC、高速サンプリング回路やインターフェース回路、ESD保護などの技術に注目しています。1985年に米マサチューセッツ工科大学(MIT)で電気工学の学士号、1987年に同修士号を取得しました。


Joe DiPilato