Understanding and Designing Wideband Output Networks for High Speed Digital-to-Analog Converters

Today, the demand for new IC components and technology continues to grow at alarming rates. The commercial and defense industries are leaders in this charge. Most new specifications dispatched to the semiconductor industry revolve around reduced size, weight, and power (SWaP). Here in the semiconductor industry, we meet those requirements by clever designs and ever improving technology. However, performance is still a key demand as well, especially for digital-to-analog converter (DAC) technology in the GSPS space. To keep this pace, the analog output matching network is often overlooked as a key element.

In order to provide more clarity, high frequency is considered to be over 1 GHz, and high speed is considered to be over 1 GSPS. Most importantly, the end user may incorporate an amplifier after the DAC, therefore, usable signals are less reliant on signal level, and more on noise and fidelity. In this paper, the matching components and their interconnectivity will be discussed. Particular attention will be given to the key specifications to consider when selecting a transformer or balun along with connection configuration techniques. Finally, ideas and optimization techniques will be provided to show how to achieve a wideband, smooth impedance transformation for DACs operating in the GHz region.

Setting the Stage

DACs have a wide range of uses; some of the most obvious uses include complex waveform generation at high frequency for commercial and military communications, wireless infrastructure, automatic test equipment (ATE), and radar and military jamming electronics. Once the system architect has found the right DAC, the output matching network must be considered to preserve the signal constructed. The component selection and topology become even more important as the GSPS DACs applications require operation in the super Nyquist, where the desired spectral information is in the second, third, or fourth Nyquist zone.

Intellectual Prerequisites

First, let us consider the role of the DAC and its position in the signal chain. A DAC functions much like a signal generator. It can provide single tone to complex waveforms at a range of center frequencies (Fc). Historically the Fc max is in the first Nyquist zone, or half the sample frequency. Newer DAC designs have internal clock doublers to effectively double the first Nyquist zone; we can refer to this action as “mixed mode” operation. The natural output frequency response curve of a DAC using mixed mode takes on the shape of a sinX/e^(X2) curve; see Figure 1. System architects can consult the product datasheet to understand component performance. Often performance parameters such as power level and spurious-free dynamic range (SFDR) will be listed at various frequencies. The clever system designer can extend the use of the same DAC into the super Nyquist zones mentioned earlier. It is noteworthy to mention that the expected output level will be significantly lower at higher frequencies (zones), for which many signal chains might include the additional gain block or driver amplifier after the DAC to compensate for this loss.

Figure 1. DAC Sin(x)/x Output Frequency Response vs. Mix Mode

Component Considerations—Choosing the Output Balun

The best performing GSPS DAC is only as good as the end user designs and measures. To shine the best light on a good DAC, only the best components should be selected to support the performance. Key circuit decisions have to be made at the beginning. Does the datasheet performance of the DAC provide enough output power? Will an active device be needed? Does the signal chain need to transfer from the DACs differential output to a single-ended environment? Will there be a transformer or balun? What is the proper impedance ratio for a balun? For this paper, the use of a balun or transformer will be the focus here. 

When choosing a balun, phase and amplitude imbalance should be carefully considered. Impedance ratio (voltage gain), bandwidth and insertion loss, and return loss are other important performance considerations. Designing with baluns is not always straightforward. For example, balun characteristics change over frequency, thus complicating the expectation. Some baluns are sensitive to grounding, layout, and center tap coupling. The system designer should never assume full datasheet performance of the balun to be the sole basis on which to choose it. Experience can play a huge role here, as the balun takes on a new form when pcb parasitics, external matching networks, and the converter’s internal impedance (load) also become part of the equation.

There are many additional characteristics of choosing a balun that are not covered in this paper. However, for more information on this and how to choose the right transformer or balun, see References 1 and 2 at the end of the article.

For achieving the widest bandwidth, Anaren, HYPERLABS, Marki Microwave, Mini-Circuits, and Picosecond are some of the best solutions on the market today. These have patented designs that use special topologies allowing for extended bandwidth in the gigahertz region, providing a high level of balance that only employs a single device to do the job.

One final note when using a single balun or multiple balun topology: layout plays an equally important role in phase imbalance as well. Keeping performance optimized at higher frequencies means keeping the layout as symmetric as possible. Otherwise, slight mismatches in traces on the front-end designs that use a balun can be proven useless and even order dynamic range limiting.

Output Match

Frequency dependent components, such as shunt capacitors and series inductors, will always limit bandwidth. That said, it might be more useful to consider the term optimization rather than match. The ultrawide bandwidths of today’s baluns would be nearly impossible to match across a multi-octave spectrum. Optimization of the above mentioned parameters requires an in-depth understanding of the system end use. For example, does the circuit try need to provide the maximum transfer of power with less concern given to SFDR? Or is the highest linearity design needed with high emphasis on SNR and SFDR, and less focus on output drive strength from the DAC? This means each parameter should have a particular weight of importance per application. Here, in this example, the output network for the AD9129 GSPS DAC is shown (Figure 2). Each resistor and the balun in the network was varied. However, as each of the resistor values are varied, the performance parameters will change, as shown in Table 1.

Figure 2. AD9129 DAC Output Front-End Block Diagram

Table 1. Case Data Definition
DAC Optimization Balun R1/R2 (Ω) R3/R4 (Ω)
Case 1 TC1-33-75G2 + (1:1 Z Ratio) DNI 50
Case 2 BAL-0006SMG (1:2 Z Ratio) 100 50
Case 3 BALH-0006SMG (1:1 Z Ratio) 100 50

The reader should note there is very little difference in the optimization component values. The most significant variant is the balun component. The data below in Figure 3 reveals the optimization in the broadband noise output mode of the DAC. In this mode, the DAC simply generates tones in the full available spectral bandwidth. The original case shows reduced available power in the first Nyquist zone and great potential for alias tones in the second, third, and fourth Nyquist zones. Case 2 shows increased output levels in the first and second Nyquist zones, and less power available in the upper Nyquist regions. Finally, optimization Case 3 appears to have good output power available in the first and second Nyquist zones while keeping the available power in zones three and four to a minimum as compared to Case 1.

Figure 3. DAC Performance in Broadband Noise Mode

Figure 4 and Figure 5 show the data recorded when the DAC is in single tone mode. Figure 5 shows the output power level at various frequencies across multiple Nyquist zones. Figure 4 shows the SFDR of the various cases vs. the DAC output frequency. The reader should develop a better understanding of the trade-offs or weighted parameter planning that needs to be understood and optimized at the onset of the design process. It should be clear that Case 1 can be improved upon by replacing it with a wider band balun solution, as in Case 2, thus yielding increased power levels in the second Nyquist zone and improved SFDR. Additionally, when the 1:2 wideband balun is implemented, Case 3, the improved power levels are maintained while further improving the SFDR of the system. Other noteworthy findings are the existence of SFDR sweet spots near 1900 MHz. This performance is independent to the output components, and is due to the internal impedance of the DAC.

Figure 4. SFDR Performance Comparison

Figure 5. Output Power Level Comparison

Conclusion

The recent development of GSPS DACs allows designers to skip multiple mixing stages in the transmit signal chain and proceed directly to the desired RF bands. When using a GSPS DAC, careful consideration must be given to the output network. It is not easy to cover all the specifics when designing a high speed, high resolution converter layout. When transforming from the differential environment of the DAC output to the single-ended RF output, special attention should be given to the balun selection. Additionally, when designing the output network of a GSPS DAC, attention should be given to the layout and topology of the network; trace widths and lengths are very important parameters to optimize. Remember, there are many parameters that need to be met in order to satisfy a match for your particular application.

References

Kester, Walt. Analog-Digital Conversion: Seminar Series. Analog Devices, Inc., 2004.

“Optimizing Data Converter Interfaces.” High Speed Systems Application. Analog Devices, Inc., 2006.

Author

Jarrett Liner

Jarrett Liner

Jarrett Liner is an RF systems application engineer with Analog Devices, Inc., in the Aerospace and Defense Group in Greensboro, NC. He has significant experience in the area of RF system and component design.

Formerly, Jarrett was an applications engineer for GaN on SiC amplifiers for the military and aerospace sector. His prior experience also includes design and test of RF IC WLAN power amplifier and front-end modules for 13 years. He served 6 years in the United States Navy as an electronics technician. Jarrett received his B.S.E.E. from North Carolina Agricultural and Technical State University located in Greensboro, NC, in 2004.

When Jarrett isn’t simulating circuit solutions or taking data in the lab, he might be found mountain biking, teaching cycle class at the gym, running, or chasing his four kids around the yard.