For applications using larger value supercapacitors (tens to hundreds of farads), a charger circuit with a relatively high charging current is needed to minimize the recharge time of the system. Supercapacitors are used as energy hold up devices in applications such as solid state RAID disks, where information stored in high speed volatile memory must be transferred to non-volatile flash memory when power is lost. This transfer time may take minutes, requiring hundreds of farads to hold up the power supply until the transfer is complete. The requirement for the recharge time of these banks of supercapacitors is typically less than one hour. To accomplish this, a high charging current is required. This article describes a supercapacitor charging circuit using the LT3663 that meets these difficult requirements.
The LT3663 is a 1.2A, 1.5MHz step-down switching regulator with output current limit ideal for supercapacitor applications. The part has an input voltage range of 7.5V to 36V, has adjustable output voltage and adjustable output current limit. The output voltage is set with a resistor divider network in the feedback loop while the output current limit is set by a single resistor connected from the ILIM pin to ground. With its internal compensation network and internal boost diode, the LT3663 requires a minimal number of external components.
Power Ride-Through Application
A procedure for selecting the size of the supercapacitor is outlined in the September 2008 edition of Linear Technology, in an article titled “Replace Batteries in Power Ride-Through Applications with Supercaps and 3mm × 3mm Capacitor Charger.” The procedure determines the effective supercapacitor (CEFF) capacitance at 0.3Hz, based on the power level to be held up, the minimum operating voltage of the DC/DC converter supporting the load, the distributed circuit resistances including the ESR of the supercapacitors, and the required hold up time.
Once the size of the supercapacitor is known, the charging current can be determined to meet the recharge time requirements. The recharge time (TRECHARGE) is the time required to recharge the supercapacitors from the minimum operating voltage (VUV) of the DC/DC converter to the full charge voltage (VFC) of the supercapacitors. The voltage on the individual supercapacitors at the start of the recharge cycle is the minimum operating voltage divided by the number (N) of supercapacitors in series. From here on, this article describes an application with two supercapacitors in series. The recharge current (ICHARGE) is determined by the capacitor charge control law:
This assumes that the voltage across the supercapacitor doesn’t discharge below the VUV/N value. This assumption is valid if the time period while input power isn’t available is such that the supercapacitor’s leakage current hasn’t significantly reduced the voltage across the capacitor. The voltage across the supercapacitor may actually rise slightly after the DC/DC converter shuts down due to the dielectric absorption effect. The initial charge time TCHARGE for a fully discharged bank of supercapacitors is:
Figure 1 shows a block diagram of the components for this supercapacitor charger application.
Charging Circuit Using the LT3663
To set the charging current, a resistor RILIM is connected from the ILIM pin of the LT3663 to ground. Table 1 shows the nominal charging currents for various values of RILIM.
|Charging Current (A)||RILIM Value (kΩ)|
The full charge voltage is set by the resistor divider network in the feedback loop. Table 2 shows various full charge voltages versus the value of RFB2 (resistor from the FB pin to ground) when resistor RFB1 (resistor tied between the VOUT pin and the FB pin) is 200k. Figure 2 shows the charging circuit for each supercapacitor.
|Full Charge Voltage (V)||RFB2 (kΩ)|
Control Circuit for Charging Supercapacitors
The control circuit in Figure 3 is used to balance the voltages of the supercapacitors while they are charging. This is accomplished by prioritizing charge current to the lower voltage supercapacitor—specifically by enabling the charging circuit for the supercapacitor with the lower voltage while disabling the circuit for the other supercapacitor.
If the top charging circuit is enabled while the bottom charging circuit is disabled, the bottom supercapacitor is charged by the input return current from the top charger. This return current is a fraction of the charging current so the top supercapacitor charges faster. The control circuit consists of a 3.3V LDO (U6) and a precision 1.25V reference (U7). U1 and U2 are configured as difference amplifiers with a gain of one to measure the voltage across each supercapacitor while U3 is a level shifted difference amplifier used to determine the voltage difference between the two supercapacitors. By level shifting the output of U3 to the reference voltage, the two comparators in U4 determine which supercapacitor needs charging.
An additional pair of level shifting resistors (R14 and R15, R16 and R17) are used to allow both supercapacitors to charge when they are within a 50mV window. When both supercapacitors are being charged, the bottom supercapacitor charges faster because it is being charged by its charging current plus the input return current of the top charger. This effect can be seen in Figure 4. The enable signal of the bottom charger is toggling as the bottom supercapacitor is being charged faster than the top supercapacitor to maintain the 50mV difference between the two supercapacitors. Figure 5 shows the effect of a 2-to-1 mismatch in capacitance value where the top is a 50F supercapacitor and the bottom is a 100F. Here the voltage on the bottom supercapacitor rises more slowly and the top supercapacitor charger enable signal toggles to allow it to maintain voltage balance.
The LT3663 allows for a low component count supercapacitor charging circuit with adjustable full charge voltage and adjustable current limit ideal for larger value supercapacitors. A control circuit can monitor and balance the voltage across each supercapacitor, even if the supercapacitors are grossly mismatched in capacitance or initial voltage.