TFT-LCDs dominate the automotive display market and are entering a very competitive phase as new technology emerges. Displays greater than 10 inches need a TFT-bias to resolve the added power needs stemming from increased size and resolution. In this design solution, we show how to develop a functional circuit given common TFT-LCD design considerations using the MAX25221. This TFT-LCD power supply IC with VCOM buffer provides a balance of a robust solution, minimal solution size, good configurability, and preprogramming options.
The modern car contains numerous displays ranging from implementation in instrument clusters to center-stack touchscreens (Figure 1), rear-seat entertainment, and more. The vast automotive display market is dominated by TFT-LCD technologies while OLEDs may play a significant role in the future. In this highly competitive scenario, TFT-LCDs have high current and precision needs.
Figure 1. Modern car center-stack touchscreen.
Typical TFT-LCD Display System
Figure 2 illustrates the simplified block diagram of a typical automotive display. The display receives power through multiple rails and the video signal through the gigabit multimedia serial link (GMSL), converting serial LVDS data to a parallel interface in RGB format. A high-voltage buck converter provides the main 5V or 3.3V rail feeding the rest of the low-voltage circuits, while the high-voltage LDO provides the always-on power to the MCU. However, as the size and resolution of the TFT-LCD increase, the panel power consumption and voltage precision become even more important for proper display control.
Figure 2. TFT-LCD display simple block diagram.
Automotive display sizes and resolution are increasing. Therefore, even when the main solution contains a source driver or TCON, the TFT-bias block is a core component in an automotive display solution that helps solve added power needs. Figure 3 illustrates the detailed TFT-bias block diagram circuitry when utilizing a TFT-bias device such as the MAX25221. The MAX25221 addresses several of the common design challenges that display modules face. First, it provides higher current for bigger displays. Second, it supplies a programmable VCOM voltage which mitigates the difficulty in tuning to varying VCOM needs from panel to panel. This VCOM coupled with diode elimination through synchronous AVDD and integrated VGON diodes all lead to minimal component needs or multi-chip solutions. The MAX25221 continues to rise above the competition by offering 2.1MHz switching and robust spread spectrum to reduce electromagnetic interference (EMI). Finally, the MAX25221 supplies both positive and negative AVDD source voltages. Panels with bipolar AVDD source voltages allow for the reference voltage of the panel (VCOM) to remain near zero rather than half of the unipolar AVDD value which creates a net-zero effect on the pixels. This net zero effect is important to reduce image retention issues. The bipolar AVDD source voltage supplies are often associated with higher-performance panels such as low-temperature polysilicon (LTPS) panels.
Figure 3. TFT-bias detailed block diagram.
Table 1. Design Parameters
|Input Voltage Range||3V to 3.6V|
|Boost Output Voltage/Current||6.8V/0.2A|
|Inverter Output Voltage/Current||-6.8V/-0.2A|
|VCOM||-0.5 to +0.5V|
Table 2. List of Components
|CINPUT||2x10µF||Capacitor, Ceramic, 6V, X7R|
|L1||2.2µH||Inductor, +20%, 2.3A|
|L2||4.7µH||Inductor, +20%, 2.3A|
|CAVDD||2.2µF||Capacitor, Ceramic, 25V, X7R|
|CNAVDD||10µF||Capacitor, Ceramic, 25V, X7R|
|CHVINP||10µF||Capacitor, Ceramic, 10V, X7R|
|COUTINV||10µF||Capacitor, Ceramic, 10V, X7R|
|CVGON||1µF||Capacitor, Ceramic, 16V, X7R|
|CVGOFF||1µF||Capacitor, Ceramic, 16V, X7R|
|CF1||22nF||Capacitor, Ceramic, 16V, X7R|
|CF2||22nF||Capacitor, Ceramic, 16V, X7R|
|DNAVDD||Schottky||Diode, 2.25A peak|
Detailed Design Procedure
Selecting the appropriate component types and values ensures optimum device operation and allows the attainment of maximum efficiency and lowest noise operation. The following sections describe how to make critical design component selections and use I2C to control key parameters according to the application circuit example shown in Figure 4.
Figure 4. MAX25221 application circuit.
Switching Frequency Selection
The switching frequency of the boost and inverting converters, as well as the charge pumps, is set using I2C to control the fSW bit in the CONFIG register. When fSW is 0, the switching frequency is 2.1MHz. When fSW is 1, the switching frequency is 420kHz. The switching frequency can have spread-spectrum frequency dithering applied to improve EMI performance using the en_ss bit in the CONFIG register.
For this design, ensure the fSW bit in the CONFIG register is set to 0 for a switching frequency of 2.1MHz.
Selection of Output Voltages
The output voltage on AVDD is set by using I2C to write a 6-bit value to avdd[5:0] in the AVDD_SET register. For this design, use a value of 0x1A to set the boost output voltage to 6.8V.
The negative source-driver supply voltage (NAVDD) is automatically tightly regulated to the boost output voltage (AVDD). It cannot be adjusted independently.
The voltage outputs of the charge pumps, VGON and VGOFF, are set respectively by writing to the vgon[5:0] and vgoff[5:0] fields in the VGON and VGOFF registers. For this design, use a value of 0x16 to set the VGON to 12V and use a value of 0x16 to set VGOFF to - 10V.
Boost Converter Inductor Selection
Three key inductor parameters must be specified for operation with the device: Inductance value (L), inductor saturation current (ISAT), and DC resistance (RDC).
To determine the inductance value, first select the ratio of inductor peak-to-peak ripple current to average output current (LIR). A good compromise between size and loss is to use a value between 0.3 and 0.6 for the LIR ratio. However, the AC characteristics of the inductor core material and the ratio of the inductive resistance to other power path resistances can influence the selection of LIR. If thin high-resistance inductors are used, as is common for LCD-panel applications, the best LIR may lie between 0.5 and 1.0. Further LIR selection can be optimized depending on operating regions and load variations. After selecting LIR, the inductance value is determined as follows:
where VIN is the input voltage, VOUT is the output voltage, IOUT is the output current, IIN is the calculated average boost input current, ? is the efficiency of the boost converter, D is the duty cycle, and fSW is the switching frequency. The inductor's saturation rating must exceed the maximum current limit of 2.25A.
Using a LIR of 0.7 and an efficiency of 90% the calculated inductor value is 2.5µH. Converting this value to the nearest standard value, use a value of 2.2µH for this design.
Inverting Regulator Inductor Selection
The inductance value for the inverting regulator can be selected using the following formulas:
where VIN is the input voltage, VNEG is the negative output voltage, INEG is the output current, LIR is the desired inductor ripple ratio, and fSW is the switching frequency.
The inductor's saturation current rating must exceed the maximum current-limit of 2.25A.
Using a LIR of 0.9 the calculated inductor value is 5.9µH. We use a value of 4.7µH for this design.
Input Capacitor Selection
The function of the input capacitor is to maintain a steady input voltage to the IC. Sufficient input capacitance must be used to avoid input voltage drop when transients are encountered on the AVDD or NAVDD outputs and when the AVDD switch is closed. If the IN voltage drops below 2.57V, the device will likely reset. Therefore, input capacitance must prevent this from happening. The total value of capacitance depends on the expected transients and the series resistance in the IN connection. An input capacitance consisting of two parallel 10µF ceramic capacitors is a good starting value for this design. Adding a lower-value (0.1µF) ceramic capacitor between the input and ground can also help to absorb high-frequency currents.
The primary criterion for selecting the output filter capacitor is low effective series resistance (ESR). The product of the peak inductor current and the output filter capacitor's ESR determine the amplitude of the high-frequency ripple seen on the output voltage.
On the boost output, HVINP, use a ceramic capacitor of at least 22µF at 420kHz and 10µF at 2.1MHz to ensure stability. Output ripple can be further reduced by increasing the output capacitance while ensuring a low ESR.
To avoid a large drop on HVINP when AVDD is enabled, the capacitance on the HVINP node should be at least 3 times larger than that on AVDD.
In this design, we select a 10µF capacitor for use on the HVINP pin while we place 2.2µF on AVDD.
The primary criteria for selecting the NAVDD output filter capacitor are low ESR and capacitance value as this capacitor provides the load current when the internal switch is on. The voltage ripple on the NAVDD output has two components: ripple due to ESR and ripple due to bulk capacitance.
A 10µF ceramic capacitor is needed on the NAVDD output to ensure stability. Increasing this outut capacitance reduces output ripple further.
Gate-Driver Power Supplies
For the positive charge pump, use 22nF "flying" capacitors, CF1 and CF2, connected between FC2+/FC2- and between FC1+/FC1-. An output capacitor of 1µF is a good starting point for this design to limit output ripple. For example, with an output current of 2mA, the output ripple due to the load current with a 1µF output capacitor will be limited to 1mV peak-to-peak at 2.1MHz.
The negative charge pump uses external flying capacitors and diodes. In this application, two flying capacitors are needed with values of 1µF.
The output ripple can be estimated using the following equation:
The VCOM output voltage is programmed using I2C to a value between -2.49V and +1V. This value can also be stored in nonvolatile memory to reduce delays at startup. The most-significant bits of the VCOM voltage setting are in the VCOM25 register while the least-significant bit is the vcom25_0 bit in the DELAY-DELAYVCOM_LSB register. To calculate the value to write to the VCOM25 register, use the following equation:
For this design, set a value of 100mV on VCOM by writing 1 to the vcom25_0 bit and 0xBD to the VCOM25 register.
NAVDD External Diode Selection
For the NAVDD external diode, the peak current rating should be at least equal to the LXN current limit (2.25A). The diode breakdown-voltage rating should exceed the sum of the maximum VINN and the absolute value of VNAVDD. A Schottky diode improves the overall efficiency of the converter.
The MAX25221 includes an I2C 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the IC and the master at clock rates up to 400kHz. The master, typically a microcontroller, generates SCL and initiates data transfer on the bus.
|ADD Pin||Device Address||8-Bit Write Address||8-Bit Read Address|
A master device communicates with the MAX25221 by transmitting the correct Slave ID with an appended R/W bit, followed by the register address and data word (for a write transaction only). Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse.
The IC's SDA line operates as both an input and an open-drain output. A pullup resistor greater than 1kO is required on the SDA bus. In general, the resistor should be selected as a function of bus capacitance such that the rise time on the bus is not greater than 120ns. The IC's SCL line operates as an input only. A pullup resistor greater than 1kO is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. In general, for the SCL-line resistor selection, the same recommendations as for SDA apply. Series resistors in line with SDA and SCL are optional. The SCL and SDA inputs suppress noise spikes to ensure proper device operation even on a noisy bus.
The MAX25221 includes five blocks of one-time programmable memory. The user can store the block of volatile registers from 0x07 to 0x15 in nonvolatile memory.
The contents of the nonvolatile memory are protected by a single-error correction/double-error detection (SECDED) redundant code while data transfer from nonvolatile memory to registers 0x07 to 0x15 is protected by a parity check. To store the contents of registers 0x07 to 0x15 to nonvolatile memory, connect a voltage source of 8.5V ±2% capable of supplying more than 25mA to the VPROG pin. When the VPROG voltage is stable, write to the burn_otp_reg register. After an NV write command is executed, the nv_flt bit should be checked.
Connect VPROG to GND if nonvolatile memory is not used.
The MAX25221 starts up with the pre-programmed values when power is applied and the EN pin is taken high. To select stand-alone mode, leave the ADD pin disconnected. In this mode, the I2C interface is not available and the FLTB pin outputs a PWM signal if a fault occurs.
TFT-LCDs dominate the automotive display market and are entering a very competitive phase as new technology emerges. Displays greater than 10 inches need a TFT-bias to resolve the added power needs stemming from increased size and resolution. In this design solution, we demonstrated how to develop a solution using MAX25221 to a given common TFT-LCD requirement. It provided a robust solution with minimal solution size, great configurability, and preprogramming options.
Learn More:MAX25221 Automotive 4-Channel TFT-LCD Power Supply with VCOM Buffer