Interference from an analog-to-digtal converter's digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. This effect is more pronounced with high speed ADCs where high speed transitions at the outputs mean that even a tiny coupling factor can cause unwanted tones in the ADC output spectrum.
By randomizing the digital output before it is transmitted off chip, we can avoid the most troublesome digital output transitions - namely the transition from all ones to all zeroes that occurs at the mid-scale input voltage. The digital output is randomized by applying an exclusive‑OR logic operation between the LSB and all other data output bits, reducing the unwanted tone amplitude.
With the digital output randomizer enabled, as long as the LSB is smaller than the noise, the readings will be randomized. To decode, the reverse operation is applied in the FPGA/ microprocessor—an exclusive-OR operation is applied between the LSB and all other bits.
The conversion data LSB (D0), the underflow/overflow bit (OF) and the clock output (CLKOUT) are not affected. The output randomizer is enabled by setting the appropriate bit in the ADC's data format register.