Developing an Electronic Toll Collection Roadside Unit Module with an RF Transceiver

Introduction

In 2019, electronic toll collection (ETC) applications saw an explosion of growth in China due to government policy. The number of cars with on-board units (OBUs) installed increased from 80 million to 200 million in just one year. Along with this OBU installation boom, the use of ETC applications was extended from expressway to city for things such as parking charges and vehicle information collection. Currently, the parking charge and vehicle information collection systems are camera based, so for ETC applications in city settings, it is desirable to integrate the ETC roadside unit (RSU) into the camera system. This article describes an ETC RSU module implementation using the AD9361 radio frequency (RF) transceiver. Its target applications are China’s ETC RSUs, which means it must comply with the Chinese standard GB/T 20851-2019 “Electronic Toll Collection—Dedicated Short Range Communication.”1 The module is of quite compact size, 11 cm × 6 cm, so it is easy to integrate inside the camera system. What’s more, this ETC RSU module can also be configured as a simple RF instrument, which could be used to test the ETC RSU module in a customer’s production line. Customers would not need an expensive RF instrument in their production line, resulting in huge cost savings.

Standard Summary

According to the GB/T 20851-2019 standard, the ETC RSU physical layer requirement is summarized in Table 1 and Table 2.

Table 1. ETC RSU Downlink Physical Layer Key Requirement Summary
Parameter Description
Carrier frequency Channel 1: 5830 MHz
Channel 2: 5840 MHz
Occupied bandwidth (OBW) ≤5 MHz
Frequency tolerance ±10 × 10-6
EIRP ≤33 dBm
Spurious emission 30 MHz to 1 GHz ≤–36 dBm/100 kHz
2400 MHz to 2483.5 MHz ≤–40 dBm/1 MHz
3400 MHz to 3530 MHz ≤–40 dBm/1 MHz
5725 MHz to 5850 MHz* ≤–33 dBm/100 kHz
Other frequency: 1 GHz to 20 GHz ≤–30 dBm/1 MHz
Adjacent channel leakage ratio ≤–30 dB
Modulation type ASK
Modulation depth 70% to 90%
Data coding FM0
Bit rate 256 kbps
Bit rate accuracy ±100 × 10-6
*2.5 times carrier bandwidth away from carrier frequency
Table 2. ETC RSU Uplink Physical Layer Key Requirement Summary
Parameter Description
Carrier frequency Channel 1: 5790 MHz
Channel 2: 5800 MHz
Frequency tolerance ±200 × 10-6
Receiver sensitivity ≤–70 dBm
Maximum input power ≥–20 dBm
In-channel interference rejection ratio <+10 dB
Adjacent channel interference rejection ratio <–20 dB
Blocking rejection ratio <–30 dB
Receiving bandwidth Channel 1 Channel 2
Max: 5787.5 MHz
to 5792.5 MHz
Max: 5797.5 MHz
to 5802.5 MHz
Min: 5788.5 MHz
to 5791.5 MHz
Min: 5799.5 MHz
to 5801.5 MHz
Modulation type ASK
Modulation depth 70% to 90%
Data coding FM0
Bit rate 512 kbps
Bit rate accuracy ±100 × 10-6

AD9361-Based ETC RSU Solution

A block diagram for an AD9361-based ETC RSU module is shown as Figure 1. The front view and back view are shown as Figure 2.

Figure 1. ETC RSU module block diagram.

Figure 2. ETC RSU module front view and back view.

Analog Devices’ AD9361 is a highly integrated RF transceiver capable of being configured for a wide range of applications. The device integrates all RF, mixed-signal, and digital blocks necessary to provide all transceiver functions in a single device.

It is worth highlighting that the AD9361 has several features that are very useful in ETC RSU applications.

Firstly, in both the transmit path and the receive path, the AD9361 integrates programmable polyphase FIR filters, which means that all digital domain filtering can be done inside the AD9361, rather than in the FPGA. This saves a lot of FPGA resources, and a lower cost FPGA can be chosen. For example, to meet the receiving bandwidth requirement, a customer could use the Filter Wizard tool provided by Analog Devices to design and tune the FIR filter response, and then get the filter coefficient to download into the AD9361.

Secondly, the AD9361 has the DCXO feature, which means that the AD9361 integrates the capacitor for the external crystal. The AD9361 is capable of tuning the capacitor, which means that the AD9361 can control the external crystal frequency very precisely. In general implementation, the customer adjusts the RF PLL N divider to meet the RF frequency tolerance requirement, but it depends on the crystal performance to meet the bit rate accuracy requirement, and it is not adjustable. For an AD9361-based solution, the customer can use the DCXO feature to tune the crystal frequency to meet the bit rate accuracy and RF frequency tolerance at the same time. And it is feasible to make a lookup table to compensate the crystal frequency temperature drift to guarantee the ETC RSU module meets the frequency tolerance and bit rate accuracy requirement in the whole working temperature range.

Thirdly, the AD9361 implements the receiver AGC functions. It has two modes—slow AGC and fast AGC. It is totally automatic, and the customer does not need to implement any receiver gain control function in the FPGA at all. The fast AGC mode is quite useful in ETC RSU applications, and it is tested so that the gain adjustment settles down in the several beginning symbols of the uplink pilot signal.

For the transmit path, first the FPGA sends the transmitter digital baseband signal to the AD9361. Inside the AD9361, the digital baseband signal is first filtered and interpolated from 10.24 MSPS to 163.84 MSPS. Secondly, the DACs convert the digital baseband signal to analog baseband signal and then it is low-pass filtered. Thirdly, it is upconverted to an RF signal of 5.83 GHz for Channel 1 or 5.84 GHz for Channel 2. In the transmitter RF domain, the AD9361 integrates an attenuator, which can control the AD9361’s transmitter output power in a greater than 80 dB range. The attenuator can be used to adjust the transmitter output power level as well as gain temperature compensation of the whole transmitter link. Then the transmitter signal is fed into the power amplifier (PA) inside the front-end module (FEM), and it is further amplified and then goes through a microstrip low-pass filter (LPF) to reject the harmonics to meet the transmitter spurious emission requirement, and finally the signal feeds to the antenna. In our ETC RSU module design, the output power at the antenna port could reach 29 dBm with the AD9361’s transmitter attenuation set as 8 dB, which means the AD9361 has enough attenuation dynamic range to compensate both high temperature gain decrease and low temperature gain increase.

For the receive path, first the RF signal from the antenna goes through the LPF and then feeds to the low noise amplifier (LNA) inside the FEM, and then it goes through a band-pass filter (BPF) to reject out-of-band interference signals. Inside the AD9361 receive path, it is further amplified and then downconverted to analog baseband. The analog baseband signal is low-pass filtered, and then the ADC converts it to digital baseband signal. In the digital domain, the signal is filtered to meet the receiving bandwidth requirement and decimated from 163.84 MSPS to 10.24 MSPS. Then the AD9361 sends the signal to the FPGA.

For the power solution, the module input voltage is 5 V. The ADP5014 combines four high performance, low noise buck regulators. It converts 5 V to 3.3 V, 2.5 V, 1.8 V, and 1.3 V. The input 5 V and the ADP5014’s four output voltages provide all the voltage rails for the FEM, AD9361, FPGA, and MCU.

Transmitter Test Results

All the transmitter test cases defined in the standard were tested, and the AD9361-based ETC RSU module passed the test with great margin. Several key test cases are screen captured as Figure 3 to Figure 6.

Figure 3. Output power of 29 dBm.

Figure 4. Modulation depth of 90%.

Figure 5. ACLR of –50 dBc.

Figure 6. Occupied bandwidth of 3.4 MHz.

Receiver Test Results

All the receiver test cases defined in the standard were tested, and the AD9361-based ETC RSU module passed the test with great margin. For the receiver sensitivity test, an FM0 coding, ASK modulated signal is downloaded into the signal generator. The demodulation algorithm is implemented inside the FPGA.

The ETC RSU module receiver sensitivity is –95 dBm, which is much better than the required –70 dBm. Figure 7 is the I/Q data FFT plot and the I/Q data magnitude plot with an input signal of –95 dBm. It is shown that the signal still has quite good SNR when the input signal level is –95 dBm.

Figure 7. I/Q data FFT plot (top) and I/Q data magnitude plot (bottom) with input signal level of –95 dBm.

For other test cases such as maximum input power, receiving bandwidth, in-channel interference rejection, adjacent channel interference rejection, and blocking rejection, the module passed all the tests.

The Simple RF Instrument Implementation

This ETC RSU module could be configured as a simple RF instrument to test the ETC RSU module and the antenna module in a customer’s production line.

The AD9361 has two RF channels. One channel is used to implement the ETC RSU module, and the other RF channel, together with an on-board high directivity microstrip coupler, are used for the return loss test.

For the module transmitter test, the AD9361 receive signal strength indicator (RSSI) function is used. The AD9361’s RSSI function has 0.25 dB accuracy after calibration, and it is good enough to test the ETC RSU module output power.

For the module receiver test, the AD9361 output power can be calibrated at one or two power levels. Then the AD9361 internal attenuator can be used to provide a wide range of accurate output power to test the receiver.

Conclusion

A compact-sized ETC RSU module can be designed using the AD9361. Analog Devices offers the complete reference design including both hardware and firmware. It is easy to integrate this module into a camera system or use it as a standard ETC RSU module alone. It passes all the ETC RSU requirements defined in the standard GB/T 20851-2019. Even more, it could be configured as a simple RF instrument, which could be used in a customer’s production line.

References

1 GB/T 20851-2019 “Electronic Toll Collection—Dedicated Short Range Communication.”

Authors

Tairan Sun

Tairan Sun

Tairan Sun joined ADI Shanghai as a staff product applications engineer in 2017. Prior to that, he was an algorithm engineer at DJI and an architecture engineer at ZTE. Tairan received a master’s degree of science in circuits and systems from Shanghai Jiao Tong University in 2012. He also received a bachelor’s degree of engineering in electronics and information engineering from Hefei University of Technology in 2009.

Bill Wang

Bill Wang

Bill Wang is a system applications engineer in ADI Beijing, who joined ADI in 2017. Bill received a B.S. degree in optical information science and technology from Guangzhou University in 2014, and an M.S. degree in photoelectric detection technology from Huazhong University of Science and Technology in 2017.

Shawn Liu

Shawn Liu

Shawn Liu is an applications engineer, who joined ADI in 2019. He is working as part of ADI’s Central Applications Center Team, which supports ADI’s wideband RF transceiver products. Shawn received a B.S. degree from Tianjin University of Science and Technology in 2015, and an M.S. degree from Tianjin University in 2019.

Aaron He

Aaron He

Aaron He is a system applications engineer at ADI Shanghai, who joined ADI in 2017. Prior to joining ADI, Aaron worked as a senior RF engineer at Ericsson. Aaron has more than 10 years' experience working on wireless communication base station design, integration, and production test system development. Aaron received a B.S. degree in telecommunication engineering from Xi’an Jiaotong University in 2001, and an M.S. degree in microwave engineering from Huazhong University of Science and Technology in 2006.