### Abstract

Maxim has designed an easy-to-build CDMA baseband-modulation generator for circuit evaluation of our various products which design into the cellular handset transmit path. This design combines a high-density programmable logic device, a crystal oscillator, and a pair of matched low-pass filters to provide the desired quadrature output waveforms. The digital circuitry incorporated into a complex programmable logic device (CPLD) is based on the IS95 standard. A 4.9152MHz crystal oscillator drives a CY37256 CPLD to produce the 1.2288MHz digital outputs, which provides an accurate I/Q (in-phase and quadrature) bit-stream to the output low-pass filters. The performance was confirmed by measuring ACPR on the MAX2361 transmitter IC and comparing the results with the ACPR observed by using an Agilent E4433B arbitrary waveform generator as the reference signal source. The lab-measured ACPR was found to agree within 0.5dB.

This application note presents the digital portion of the CDMA reverse link waveform generator, and describes some of the design issues and how they were handled.

### Introduction

### Digital System Description

### The Textbook CDMA Generator

**Figure 1**shows the block diagram for a CDMA reverse channel generator. The CDMA generator is composed of the following items:

- The digital data source. In a cell phone, which is coded speech data.
- Encoding and interleaving functions.
- A Walsh code generator.
- A 42-bit long PN (pseudonoise) generator of maximal length, refered to here as the "long code".
- 3 modulo-two mixers or exclusive OR gates.
- Two "short code", 15-bit PN maximal length shift registers.
- A one-half chip delay, equal to (813.8ns / 2) or 406.9ns.
- A pair of matched finite impulse response (FIR) low-pass filters.

*Figure 1. Text book CDMA reverse link generator.*

### Shortcuts Taken in This Effort

**Figure 2**shows the abbreviated block diagram implemented in this effort.

*Figure 2. Implemented CDMA reverse link generator.*

### Design Details

### Walsh Code Generator

(Eq. 1) |

_{1}= 0. The lower right-hand region of the Walsh matrix, shown in Equation 1 by the W

_{n}with a bar on top, implies a bit-wise logic inversion of each entry in the matrix. Each row in the Walsh matrix can be generated with some exclusive or gates and a six-bit counter. Until this observation is made, the Walsh matrix may seem a daunting module to generate with Verilog code and fit in a CPLD. The listing of the Verilog code is included here as a sample only.

module walsh( clk, resetn, select, wout); | ||

//Walsh code generator. Selects one out of N = 64. | ||

input clk, resetn; | ||

input [5:0]select; // vector to select which walsh code is generated | ||

output wout; | ||

reg [5:0] cntval; | ||

// intermediate terms to keep output exor size small. | ||

reg [5:0] p ; | ||

reg t01, t23, t45; // these registers are used to pipeline the EXOR section | ||

reg s0, s1; // more pipeline registers for EXOR | ||

always ? (negedge resetn or posedge clk) | ||

begin | ||

if(!resetn) // Is it time to reset?? | ||

begin | ||

cntval <= 0; // initialize the counter register | ||

end | ||

else | ||

begin | ||

cntval <= cntval + 1; //Warp does an efficient job implementing this. | ||

end | ||

end | ||

always ? (negedge resetn or posedge clk) | ||

begin | ||

if(!resetn) // Is it time to reset?? | ||

begin | ||

p[5:0] <= 0; // initialize all registers associated with this section. | ||

t01 <= 0; | ||

t23 <= 0; | ||

t45 <= 0; | ||

s0 <= 0; | ||

s1 <= 0; | ||

end | ||

else | ||

begin | ||

p <= cntval & select ; | ||

t01 <= p[0] ^ p[1] ; // the ^ symbol is the exclusive OR operation. | ||

t23 <= p[2] ^ p[3] ; | ||

t45 <= p[4] ^ p[5] ; | ||

s0 <= t01 ^ t23; | ||

s1 <= t45; | ||

end | ||

end | ||

assign wout = s0 ^ s1 ; // a last bit of async. Logic to generate the final output | ||

endmodule |

- Metastability conditions are minimized.
- The logic maps efficiently into the CPLD architecture.

### PN Generators

**Figure 3**)

*Figure 3. Examples of simple and modular PN generators.*

^{15}+ X

^{13}+ X

^{9}+X

^{8}+ X

^{7}+ X

^{5}+ 1

^{15}+ X

^{12}+ X

^{11}+ X

^{10}+ X

^{6}+ X

^{5}+ X

^{4}+ X

^{3}+ 1

^{42}+ X

^{35}+ X

^{33}+ X

^{31}+ X

^{27}+ X

^{26}+ X

^{25}+ X

^{22}+ X

^{21}+ X

^{19}+ X

^{18}+ X

^{17}+ X

^{16}+ X

^{10}+ X

^{7}+ X

^{6}+ X

^{5}+ X

^{3}+ X

^{2}+ X

^{1}+ 1

module i_code_s( clock, resetn, i_code_out); | ||

// Generate the 15-bit PN code using the polynomial | ||

// x^{15} + x^{13} + x^{9} +
x^{8} + x^{7} + x^{5} + 1 |
||

input clock, resetn; | ||

output i_code_out; | ||

reg [15:1]pi; | ||

always ?(posedge clock or negedge resetn) | ||

if(!resetn) | ||

begin | ||

pi <= 15';b111111111111111; // init the shift register with ones | ||

end | ||

else | ||

begin // here starts the modular shift register | ||

pi[1] <= pi[15]; | ||

pi[5:2] <= pi[4:1] ; | ||

pi[6] <= pi[5] ^ pi[15]; | ||

pi[7] <= pi[6]; | ||

pi[8] <= pi[7] ^ pi[15]; | ||

pi[9] <= pi[8] ^ pi[15]; | ||

pi[10] <= pi[9] ^ pi[15]; | ||

pi[13:11] <= pi[12:10]; | ||

pi[14] <= pi[13] ^ pi[15]; | ||

pi[15] <= pi[14]; | ||

end | ||

assign i_code_out = pi[15]; | ||

endmodule |

*Figure 4. CDMA generator schematic.*

### Results

#### References and Resources

- R.C. Dixon,
*Spread Spectrum Systems*. New York: John Wiley & Sons, 1976 - David P. Whipple, "North American Cellular CDMA",
*Hewlett-Packard Journal*, December 1993, pp. 90-97 - Ken Coffman,
*Real World FPGA Design with Verilog*. Upper Saddle River: Prentice Hall PTR, 1999, ISBN 0-13-099851-6 - Samir Palnitkar,
*Verilog HDL, A Guide to Digital Design and Synthesis*Sunsoft Press/Prentice Hall, 1996, ISBN 0-13-451675-3 - Special thanks to Lane Hauck at Cypress Semiconductor for his advice and guidance in learning Verilog and the nuances of CPLD design.
- Special thanks for Dave Devries of Maxim Integrated for his collaboration and certain key insights during this project.