Abstract

This application note describes how to set control loop compensation for the MAX20796 multiphase, current-mode high power-density converter with an optional MAX20766 power-stage, to optimize frequency-domain and transient-response performance.

Introduction

The MAX20796 is a current mode control converter which can be configured in a two-phase or three-phase operation. This application note provides guidelines about selecting control loop parameters for MAX20796 to optimize the steady state, frequency domain, and transient load step performance.

Defining Power Stage and Loop Performance Parameters

For this use case, the compensation parameters for the MAX20796 are chosen as follows:

Power Stage Parameters:

Input Voltage: V_IN = 12V

Output Voltage: V_OUT = 0.8V

Duty:

Number of phases: N_PH = 3

Switching Frequency: F_SW = 400 kHz

Switching time period:

Steady state load current: I_OUT = 80A

Steady state voltage ripple: ΔV_{PK_STEADYSTATE} = 2% V_OUT = 0.016V

To design an optimal compensation loop, first select the transient and frequency domain performance expected from the power converter design. For this example, the V_OUT must not soar or droop by more than 3% in response to a 30% load change with a slew rate of 10A/µs.

Load Transient specifications:

I_STEP = 30% (I_OUT) = 24A

ΔV_{pk_Soad_Droop} = 3 % V_OUT = 0.024V

The MAX20796 compensation design recommends choosing the voltage loop bandwidth to be in the range of f_SW/5 to f_SW/10 to achieve a fast time-domain response. In this use case example, the desired bandwidth chosen is f_SW/5 = 80kHz. Choosing a bandwidth higher than f_SW/4 reduces the overall system stability because of the influence of high frequency poles.

Desired Voltage Loop Bandwidth:

Choosing Inductor and Output Capacitor Values

Coupled inductors have an immense advantage for achieving high power density solutions for multiphase designs. Compared to equivalent discrete inductors, coupled inductors produce a smaller per-phase ripple, which results in higher efficiencies. For this use case example, a coupled inductor with a per-phase inductance (L_K) of 100nH is selected.

The output capacitor is selected based on the following criteria:

• Steady State (_{COUT_STEADY_STATE}): The amount of peak-to-peak voltage ripple supported during a steady state operation. The equation for this criterion does not incorporate the ESR effect of the capacitor.

where ΔVI_Total is pk-pk ripple of the sum of currents in all phaseed and is calculated as:

Note: This equation is applicable for operation with

The pk-pk ripple current is the same for a coupled inductor and a discrete inductor (of equal inductance value), so the calculation for C_{OUT_STEADY_STATE} is independent for either inductor.

• Transient: A suitable capacitor must be chosen such that the magnitude of the soar/droop in V_OUT in response to a step change in the load is within the desired specifications. The following two transient criteria must be evaluated to determine optimum capacitance:

• Transient Criteria 1: Calculate the capacitance (C_{OUT_TRANSIENT_CRITERIA1}) to evaluate whether the inductor is sufficient to supply a charge (ΔQ_{CAP_DEMAND}) during a load-step transient.

  

  

• Transient Criteria 2: Model a control loop to attain a desired bandwidth value to calculate the capacitance (C_{OUT_TRANSIENT_CRITERIA2}) to meet the soar/droop specification in response to a load step.

  

Note: The equation for C_{OUT_TRANSIENT_CRITERIA2} is based on an infinite slew rate. Slew rate is finite, and the actual capacitance may be smaller than when calculated by the formula above.

Choose the largest value among the three criteria (C_{OUT_STEADY_STATE}, C_{OUT_TRANSIENT_CRITERIA1}, and C_{OUT_TRANSIENT_CRITERIA2}) as the final value for the output capacitance. For this design, 27 pieces of the 100µF ceramic capacitors (6.3V, 1210 size) are installed on the board to account for voltage derating characteristics of the capacitors. For a compact solution, 1206 ceramic capacitors are recommended.

Selecting Control Loop Parameters

The MAX20796 is a variant of a peak current mode controller with an outer voltage loop and an inner current loop. Both the loops have a dedicated compensator with a gain and zero location that the user can configure. The output of the current loop is the input to the modulator, which generates the pulse-width modulation (PWM) based on closed loop control action. The steps in this section provide more information about the choice of compensation.

Step 1: Select Current Loop Zero

The inductor and output capacitor generate a double pole in the frequency domain, which is calculated as f_LC.

Being a current control topology, the inductor behaves like a voltage-controlled current source, which means that the double pole at the f_LC is reduced to a single pole system. To attenuate the effect of this pole, choose the current loop zero (f_ZC) to be equal to or less than the f_LC.

Current Zero Location:

The closest available lower value for this current zero selection is chosen to be 18kHz for this system.

Step 2: Select R_INT

R_INT is the value of the resistor that defines the gain of the current loop compensator. The input to the current loop is the difference (I_ERR) between the current reference commanded by the voltage loop and the sensed current from power stage (I_TOTAL). The product of I_ERR and R_INT is defined as ΔV_RINT and should be at least greater than 0.1V to ensure immunity from background noise sources. As a good practice, the maximum value of ΔV_RINT is recommended to be 0.2V to avoid voltage headroom constraints in the modulator circuit.

Where:

ΔV_RINT is recommended to be with in 0.1V o 0.2V

K_i is the current sence gain and its value is 10⁵

The equation for R_INT chooses ΔV_RINT to be 0.2V since a larger value provides better noise immunity. The nearest R_{INT ]} value of 2209Ω is

Step 3: Select PWM_RAMP

To avoid subharmonic oscillations in a current mode control, it is a prevalent technique to add a stabilizing ramp to the sensed current. It is a good practice to choose the slope of the added ramp equal to the downslope of the sensed inductor current. With a similar principle, the minimum magnitude of PWM_RAMP (V/µs) for the MAX20796 is calculated as follows:

where:

K_IP is 1,25 and is the proportional gain of current loop compnsator

Use a value of 1.27V/µs as a suitable theoretical starting point. To provide extra noise immunity to the modulator circuit and ensure a reliable operation, the 2.55V/µs value is empirically chosen such that the switch node voltage demonstrates steady state stability in event of a load transient (on and off) event.

The following aspects must be taken into consideration before choosing a much larger PWM_RAMP than what is theoretically needed:

• For any use case, do not choose a large PWM_RAMP if it violates the modulator’s dynamic voltage span. See Step 8.
• A larger PWM_RAMP can reduce the overall bandwidth of the system. See Step 9 for ways to overcome bandwidth loss.

Note: These aspects are accurate for use cases with ON time duration around 175ns or larger. For smaller ON time, a larger PWM_RAMP is required.

Step 4: Select R_OCR

To ensure current balance between the phase currents, R_OCR is recommended to be within 3 to 5 times of the selected R_INT value. In this design example, the value of R_OCR is selected to be 11.8kΩ.

Note: By default, the device automatically sets a suitable value for R_OCR based on the pin-strap selection of R_INT. However, the user can always modify R_OCR using a PMBus™ command. If such PMBus-modified value of R_OCR is stored using STORE_INVENTORY command, thereafter, a change in R_INT will not affect the value of R_OCR.

Step 5: Select Voltage Loop Zero

In a current mode control, the output of the voltage loop provides a command reference for the operation of the current loop. In a closed loop operation, the current loop can be visualized as a mechanism that provides a constant gain between the sensed current and the commanded current.

To provide a sufficient phase margin for the power converter, the MAX20796 architecture allows the user to choose the location of the voltage loop zero (f_ZV). A lower value for voltage loop zero helps provide a larger phase bump. However, a value that is too low implies a larger time constant for the system and results in an increased recovery time for the output voltage in event of a load transient. A voltage zero value that is too high can provide a lesser phase bump (at the desired bandwidth) and reduce the phase margin. For MAX20796, setting the voltage loop zero as 1/5th of the desired voltage loop bandwidth provides the optimal performance.

For this design example, voltage zero is chosen as 10.3kHz, which is the first available pin-strap value that is lower than the calculated value.

Step 6: Select IDES_GAIN

The IDES_GAIN denotes the proportional gain of the voltage loop. A value of 0.98 (default) is used for IDES_GAIN. The MAX20796 supports increasing the value to up to 10 times the lowest value. Changing the IDES_GAIN can prove to be a convenient ‘knob’ to increase the gain of the system, which results in increased bandwidth. A ‘knob’ is handy to overcome bandwidth loss due to the following:

• The use of a larger PWM_RAMP to provide noise immunity to the system
• The use of a larger output capacitance

Step 7: Select LEAD_LAG

The MAX20796 has the option to add a lead-lag network in the voltage loop compensator to provide a 25 degree, 35 degree, or 45 degree phase bump at either 60kHz, 90kHz, 120kHz, or 160kHz. A lead-lag network helps increase the phase margin and the transient stability of the converter at the zero-cross-over frequency, also known as bandwidth.

Note: Boosting the phase margin by using the LEAD_LAG settings causes the voltage loop gain to be attenuated by 0.81, 0.54, or 0.34 depending on the selection. This results in reduced bandwidth, which can be increased by the use of a higher IDES_GAIN value.

The lead-lag network can also be configured in a pure attenuator mode that provides no phase bump. This configuration can help the converter to improve the phase margin by 5 to 10 degrees by sacrificing some bandwidth.

Step 8: Verify Voltage Headroom Sufficiency

As demonstrated in Step 1 to Step 5, the compensation parameters can be suitably calculated for a given circuit parameter and performance requirement. However, the operation with the chosen parameters must not exceed the voltage headroom margins within the IC. Use the following equation to calculate the voltage span in the circuit. The voltage span must not exceed 1.2V.

For this use case, the voltage span is 0.676V, which is well within the recommended maximum of 1.2V.

Step 9: Bench Evaluation

After selecting an initial compensation setting using Step 1 to Step 8, evaluate the choice of these parameters on the bench. The two-step iterative process is as follows:

Step 9a: Frequency Response

1. Measure the frequency response of the power converter while operating at full load.
2. Adjust compensation parameters to ensure the voltage loop bandwidth is within ±10% of f_SW/5 while maintaining a phase margin of ≥55 degrees. A few technical considerations which may prove handy while trying to meet this criterion are as follows:

• Increase or decrease the bandwidth by changing IDES_GAIN.
• Increase more capacitors to improve the phase margin. However, this may reduce the bandwidth of the system.
• Reduce the voltage loop zero to achieve a faster settling time after a load-step transient event.
• Use the LEAD_LAG settings to bump the phase margin at the cost of reducing the bandwidth.
• Use IDES_GAIN to overcome the loss of bandwidth, which is due to the use of LEAD_LAG or a higher PWM_RAMP value. Judicious use of both of these settings can help achieve the desired bandwidth and a large phase margin.

Step 9b: Transient Response

When the frequency response is observed to have a sufficient bandwidth and phase margin, apply a load-step transient and verify if the soar or droop in V_OUT is within the desired parameters.

Bench Measurements with Selected Compensation

Figure 1 shows the frequency response measured on bench (load current = 80A). The bandwidth of the converter is 83kHz, and the phase margin is approximately 56 degrees. Compared to the settings demonstrated in Step 1 through Step 8, the IDES_GAIN of 2.65 was used instead of the default setting of 0.98. Using the higher IDES_GAIN can be need for the use of a higher PWM_RAMP or larger capacitors because of an approximate derating estimation. As a result, the higher IDES_GAIN achieves a lesser bandwidth than theoretically calculated.

Figure 2 shows the transient response of the converter. In response to a 33% load step (slew rate = 10A/µs), the converter output meets the desired specification of ±3% soar/droop (±24mV) without incorporating a voltage ripple.

Use of LEAD_LAG

Figure 3 shows a bode plot for the same system used to generate Figure 1, except that the LEAD_LAG compensator is enabled to provide a phase boost of 25 degrees at 160kHz. The PWM_RAMP is increased to 3.18V/µs (compared to Figure 1, which used 2.55V/µs) to provide additional steady state stability while ensuring that voltage span is within 1.2V.

Compared to Figure 1, Figure 3 shows a better phase margin of approximately 72 degrees with the bandwidth remaining the same at approximately 80kHz.

Figure 4 shows the transient response of the system measured in Figure 3. Compared to Figure 2, the voltage soar/droop shows a more damped response because of an enhanced phase margin.

Conclusion

This application note demonstrates that the MAX20796 compensation design procedure achieves a high-performance power-conversion solution. Using formulas and practical guidelines, the MAX20796 can be easily configured to meet stringent and high-quality frequency and transient performance.

Appendix

This appendix provides a quick demonstration of a 2-phase solution realized using the MAX20796. Table 1 lists the operational parameters.

By following the compensation calculation procedure mentioned in Step 1 to Step 9, Table 2 shows the compensation parameters for the converter in Table 1.

Note: To achieve a capacitance of 1000µF, 13 x 100µF ceramic capacitors (1210-size, 6.3V) are installed to compensate for the derating of the capacitors.

Figure 5 shows the bode plot measured for the system. The bode plot achieves the desired bandwidth of approximately 80kHz and has a phase margin close to 60 degrees even without the use of LEAD_LAG settings.

Figure 6 shows the transient response for a 30% load step inflicted to the output of the regulator. With sufficient bandwidth and phase margin, the transient response is well-behaved and the soar/droop is easily within the required tolerance of ± 3%.

Usecase:

V_IN = 5V, V_OUT = 1V, N_PH = 2, F_SW = 400kHz

Inductor = 100nH coupled, Capacitors = 13 x 100uF ceramic (1210-size, 6.3V , X5R)

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