Active Voltage Positioning Designs and Considerations for General-Purpose Current-Mode Control Buck Regulators

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Abstract

Current-mode control offers several advantages over traditional voltage-mode control. These include faster dynamic response, simpler control-loop design, and fast and accurate cycle-by-cycle current limitation. To further improve load transient response while reducing output capacitance and related solution size and cost, active voltage positioning (AVP) can be integrated into the voltage regulator employing current-mode control. AVP involves actively adjusting the target output voltage in response to load current variations. This article provides a detailed explanation of AVP and the accurate derivation of the AVP circuitry implemented with general-purpose buck regulators.

Introduction

The LTM4650-2 (15V_IN/dual 25A or single 50A) series power modules integrate all power components except bulk input and output capacitors in one package, provide a high performance, high density, and easy to use solution for system designers. These modules also implement the peak-current-mode control algorithm, making it easy to be paralleled to increase the current capability. Figure 1a illustrates the load transient waveform typically observed in an LTM4650-2 application. It's crucial to maintain the output voltage within acceptable ranges, especially during load transients, to ensure the normal operation of computing cores. For instance, Intel ALTERA Arria II specifies voltage ranges varying from ±3% to ±5% for different functions.¹ Typically, voltage supplies for phase-locked loops (PLLs) and core operations have a ±3% limitation, while those for I/Os have a ±5% limitation. Given the rapid load transient speeds during computing tasks, voltage regulators with high control bandwidth or large output capacitance become necessary. Increasing output capacitance can escalate solution size and cost.

To further improve the transient performance of the LTM4650 series of products, the AVP technique presents a promising avenue as an example in Figure 1b. This article aims to elucidate the fundamental principles of AVP within the context of current-mode control and provide guidelines for designing AVP circuits.

AVP Improvement in Load Transient or Capacitance Reduction

Traditionally, voltage regulators maintain output voltage at a targeted value irrespective of changes in input voltage or load conditions. However, the voltage regulators employing AVP take a different approach by actively decreasing the output voltage when load current increases.² Figure 2 illustrates this relationship between output voltage and load current in a voltage regulator utilizing AVP.

This departure from the traditional fixed-output voltage paradigm aligns with guidelines set forth by CPU Voltage Regulator-Down (VRD) standards, which indicate that it is acceptable for the core voltage to decrease when increasing load current.³ This dynamic adjustment ensures efficient utilization of power resources and helps optimize system performance under varying load conditions.

In the AVP function, the rated nominal output voltage should be designed at the half-load (50% of Io(max)) condition. Under this setup, the output voltage varies from the rated voltage Vo +ΔV/2 at no load condition to the rated Vo -ΔV/2. Figure 3 provides an illustrative example of the output voltage waveform for a voltage regulator employing AVP. Compared to traditional voltage regulators, AVP-regulated output voltage doesn't fully recover to the original value. Consequently, during load transients, the peak-to-peak voltage can be significantly reduced, resulting in lower requirements for output capacitance. This reduction in required capacitance contributes to more efficient use of board space and cost savings in system design. Theoretically, with the rated full load step up to 50%, capacitance can be reduced with the application of AVP. Or, with the same output capacitance, the Vo p-p can be reduced by half.

AVP Circuit Design

Dedicated power controllers for processor VR applications usually have built-in circuits to implement accurate AVP (or active load line). However, even for a general-purpose current-mode control power regulator, there are several methods available to implement AVP.³ For example, the simplest methods applicable to the LTM4650-2 are depicted in Figure 4. By incorporating two resistors into the comp pin of the device without altering existing designs, AVP functionality can be achieved. In Figure 4a, the additional resistors do not affect the selection of the feedback resistor. On the one hand, the accuracy of AVP is heavily reliant on the precision of the error amplifier's transconductance (gm).⁴ On the other hand, Figure 4b illustrates another implementation method, AVP-R, which requires consideration of resistors R1, R2, Rlo, and Rhi together. Although this method increases design complexity, it eliminates the influence of the error amplifier's transconductance, gm. Given these considerations, AVP-R is preferred in LTM4650-2 designs due to ensuring more reliable and accurate voltage regulation for the core applications.

To access the AVP function in the simplest manner on the LTM4650 series of products, an Excel spreadsheet was released on LTpowerCAD^*, which can be found at the two locations shown in Figure 5.

In the spreadsheet, the detailed operation needs to be input. Following the indication of the recommended Rlo, Rhi, and the real circuit configuration, the estimated AVP function shown on the right side can be realized.

Experiment Result

1. AVP Function Verification

To verify the design method of the AVP function in LTM4650-2 applications, experiments were conducted. The experiments did not consider the thermal effects of the DC resistor (DCR) or the sensing resistor. The LTM4650-2 is configured at 500kHz switching frequency. The maximum load current was 25A. To account for the part-to-part variation, two identical boards were used in the experiments. Figure 7 shows the test with a 12V V_IN and 1V V_OUT, with a 100mV voltage drop, which is a typical condition for the LTM4650-2.

2. Output Capacitance Reduction

To further demonstrate the advantages of applying the AVP function in core-related applications, including the reduction in peak-to-peak voltage during load transients and the decrease in output capacitance, experiments were conducted using the LTM4650-2. The default output capacitors comprised 2× 470µF pos-capacitors and 5× 100µF ceramic capacitors. The AC voltage waveform during full-load step is measured at 179mV. Subsequently, utilizing the same hardware setup but with the AVP configuration, the peak-to-peak output voltage during load transients was reduced to 97.6mV, which is around 50% peak-to-peak voltage reduction. Or to achieve the same Vo p-p during the load transient, the output capacitors can be reduced by half, which is shown in Table 1. These experiments further validate the benefits of incorporating the AVP function in voltage regulator designs, showcasing the ability to reduce peak-to-peak voltage variations and minimize the requirement for output capacitance. This reduction in output capacitance translates to lower solution costs, as fewer capacitors are required for the voltage regulator design.

Meanwhile, the implementation of AVP is not limited to the LTM4650 series of products. The same method can be used in most modules with peak-current-mode control. The Excel spreadsheet can also be reconfigured for different modules.

Conclusion

This article proposes a detailed design method for implementing the AVP function on the general-purpose current-mode control buck regulators, and the LTM4650-2 is used as an example to demonstrate and verify the proposed method. By addressing the challenges posed by power component nonlinearities and leveraging the unique features of the LTM4650-2, the proposed AVP design offers an efficient and reliable solution for voltage regulation in demanding data center environments. This article provides valuable insights and practical guidance for engineers seeking to implement AVP functionality in their voltage regulator designs, ultimately improving system performance and reducing costs in core-related applications.

References

¹ Henry Zhang. "Application Note 149: Modeling and Loop Compensation Design of Switching Mode Power Supplies." Linear Technology, January 2015.

² Arria^® II Device Handbook, Volume 3: Device Datasheet and Addendum. Intel, December 2013.

³ Robert Sheehan. "Design Note 224: Active Voltage Positioning Reduces Output Capacitors." Linear Technology, 1999.

⁴ Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1. Intel, September 2009.

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