CN0241

The circuit is a classic high-side current sensing circuit topology with a single sense resistor. The other four resistors (dual 1 kΩ/20 kΩ divider) are in a thin film network (for ratio matching) and are used to set the difference amplifier gain. This amplifies the difference between the two voltages seen across the sense resistor and rejects the common-mode voltage.

V_OUT = (V_A – V_B) (20 kΩ/1 kΩ)

Figure 2 shows a simplified schematic of the ADA4096-2. The input stage comprises two differential pairs (Q1 to Q4 and Q5 to Q8) operating in parallel. When the input common-mode voltage approaches V_CC − 1.5 V, Q1 to Q4 shut down as I1 reaches its minimum voltage compliance. Conversely, when the input common-mode voltage approaches V_EE + 1.5 V, Q5 to Q8 shut down as I2 reaches its minimum voltage compliance. This topology allows for maximum input dynamic range because the amplifier can function with its inputs at 200 mV outside the rail (at room temperature).

As with any rail-to-rail input amplifier, V_OS mismatch between the two input pairs determines the CMRR of the amplifier. If the input common-mode voltage range is within 1.5 V of each rail, transitions between the input pairs are avoided, thus improving the CMRR by approximately 10 dB.

The ADA4096-2 inputs are protected from input voltage excursions up to 32 V outside each rail. This feature is of particular importance in applications with power supply sequencing issues that can cause the signal source to be active before the supplies to the amplifier are applied.

Figure 3 shows the input current limiting capability of the ADA4096-2 provided by low RDS_ON internal series FETs (green curves) compared to using a 5 kΩ external series resistor with an unprotected op amp (red curves).

Figure 3 was generated with the ADA4096-2 in a unity-gain buffer configuration with the supplies connected to GND (or ±15 V) and the positive input swept until it exceeds the supplies by 32 V. In general, input current is limited to 1 mA during positive overvoltage conditions and 200 μA during negative undervoltage conditions. For example, at an overvoltage of 20 V, the ADA4096-2 input current is limited to 1 mA, providing a current limit equivalent to a series 20 kΩ resistor.

Figure 3 also shows that the current limiting circuitry is active whether the amplifier is powered or not.

Figure 3 represents input protection under abnormal conditions only. The correct amplifier operation input voltage range (IVR) is specified in Table 2 to Table 4 of the ADA4096-2 data sheet.

The AD7920 is a 12-bit, high speed, low power, successive approximation ADC. The part operates from a single 2.35 V to 5.25 V power supply and features throughput rates up to 250 kSPS. The part contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 13 MHz.

The conversion process and data acquisition are controlled using CS and the serial clock, SCLK, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS, and the conversion is initiated at this point. There are no pipeline delays associated with the part.

The AD7920 uses advanced design techniques to achieve very low power dissipation at high throughput rates.

To enter power-down mode, the conversion process must be interrupted by bringing CS high anywhere after the second falling edge of SCLK, and before the tenth falling edge of SCLK. Once CS is brought high in this window of SCLKs, the part enters power-down mode, the conversion that was initiated by the falling edge of CS is terminated, and SDATA goes back into three-state. If CS is brought high before the second SCLK falling edge, the part remains in normal mode and does not power down. This avoids accidental power down due to glitches on the CS line.

To exit this mode of operation and power up the AD7920 again, a dummy conversion is performed. On the falling edge of CS, the device begins to power up and continues to power up as long as CS is held low until after the falling edge of the tenth SCLK. The device is fully powered up once 16 SCLKs have elapsed, and valid data results from the next conversion.

If CS is brought high before the tenth SCLK falling edge, the AD7920 goes back into power-down mode again. This avoids accidental power up due to glitches on the CS line or an inadvertent burst of eight SCLK cycles while CS is low. Although the device can begin to power up on the falling edge of CS, it powers down again on the rising edge of CS as long as it occurs before the tenth SCLK falling edge.

Further details regarding the timing can be found in the AD7920 data sheet.

Test Results

An important measure of the performance of the circuit is the amount of noise in the final output voltage measurement.

Figure 4 shows a histogram of 10,000 measurement samples. This data was taken with the CN-0241 Evaluation Board connected to the EVAL-SDP-CB1Z SDP-B evaluation board. Details of the setup are described in the Circuit Evaluation and Test section.

The power supply was set to 3.0 V, and 10,000 samples of data were acquired at the maximum rate of 250 kSPS without having turned the output of the LDO off. Figure 4 shows the results of this acquisition. The peak-to-peak noise is approximately 2 LSBs, corresponding to about 0.3 LSB rms.

The SD shutdown pin connected to the ADP3336 was then asserted low in the software causing the output of the LDO to turn off. After approximately 1 minute, the shutdown pin on the ADP3336 was then asserted high, turning the output back on, and the same number of data samples were acquired. Figure 5 shows the results of this acquisition.

Figure 5 shows that the output of the ADA4096-2 did not latch during power down when the input was held high.

A complete design support package for this circuit note can be found at www.analog.com/CN0241-DesignSupport.