Design & Integration File
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Overview

Design Resources

Design & Integration File

  • Schematic
  • PCB Layout
  • Bill of Materials
  • Allegro Layout Files
Download Design Files 16.72 MB

Description

PSE applications that deliver both power and data over ethernet to devices such as IP cameras and wireless access points require compact, efficient, and standards-compliant solutions to support increasing power demands. This reference design's wide input voltage range of 9-48V ensures compatibility with diverse and common power sources (12V/24V/48V). Its active clamp topology achieves efficiency greater than 90% at 100W of power and nominal Vin conditions. The standard half-brick form factor (2.3in x 2.4in) enables easy integration, and the strong isolation (2200Vac) provides superior industrial protection and safety.

Applications

  • PSE Applications
  • Industrial Automation
  • Smart Building Systems

Features & Benefits

  • Wide input voltage range of 9-48V ensures compatibility with diverse and common power sources (12V/24V/48V).
  • Active clamp topology achieves efficiency greater than 90% at 100W of power and nominal Vin conditions.
  • Energy loss minimized and thermal performance improved, reducing operating costs and enhancing system reliability.
  • Standard half-brick form factor (2.3in x 2.4in) simplifies system integration, saves space, and reduces design complexity.
  • Strong isolation (2200Vac) provides superior safety and protection for sensitive equipment.

Solution Specifications

Electrical Requirements:

  • External Input Voltage: 9 VDC – 48 VDC (12 V / 24 V / 48 V nominal)
  • Output Voltage: 54 VDC
  • Output Current: 2 A
  • Output Power: 100 W
  • Load Regulation: ± 1%
  • Maximum Output Ripple: 250 mVPP
  • Transient Response: ± 5% (50% to 100% Load Step)
  • Isolation: 2200 VAC

Performance Requirements:

  • Efficiency: ≥ 90%

Mechanical Requirements:

  • Transformer Type: Planar, Off-the-shelf
  • Form Factor: Half-Brick size

Important Notice and Disclaimer
Please read the Reference Design Disclaimer for Analog Devices design information and resources.

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