Features and Benefits

  • Jitter buffer accepts packets as input and give out frames as output.
  • It provides frames in proper order, even if the packet arrivals are not in order.
  • It supports concurrent payloads (different payloads occurring at the same instant).
  • Initial jitter buffer delay and maximum frames to buffer can be set using configuration parameters.
  • Target Processor: Code compatible across the Blackfin Processor Family ADSP-BF5xx.
  • Release format: Object code module with C source wrapper.
  • Input format: The library accepts the input packets to be added to jitter buffer.
  • Input buffer samples per block: User-configurable.
  • Framework dependencies: None.
  • Sample rate: 8 kHz
  • Output format: The output is frame/frames, which are written to the output structure.
  • Multi-threading: Fully re-entrant and multi-instancing capable.

Product Details

The transportation of real-time data such as voice over asynchronous packet switched networks such as ATM and the internet have gained popularity in the recent years, mostly due to the availability of new low bit-rate codecs. The use of the packet switched network for voice increases bandwidth utilization compared with the traditional connection-oriented approach and can lead to lower call costs. However, the nature of packet switched networks causes unpredictable and variable delays to speech packets, often resulting in poor unintelligible speech at the receiving end. The effect due to these delay variations or jitter can be minimized by using an Adaptive Jitter Buffer, which imposes a certain delay to each packet before playing back the packet stream at a constant rate. The module will be referred to as Jitter Buffer in this document.

Downloads And Related Software

Software Development Kit

Software Development Tools

VisualDSP++ 5.1

VisualDSP++ for Blackfin, SHARC, and TigerSHARC processors is an easy-to-install and easy-to-use integrated software development and debugging environment (IDDE) that enables efficient management of projects from start to finish from within a single interface.


Each module supports the Analog Devices, Inc. (ADI) Blackfin or SHARC Processor family and is a licensed product that is available in object code format. Recipients must sign or accept a license agreement with ADI prior to being shipped or downloading the modules identified in the license agreement.

Performance Metrics

MIPS summary:

 Code memory (KiB)
 Data RAM (KiB)
 Constant Data Tables (KiB)
 MIPS Average
 2.06 8.06 0 0.208

  • MIPS measured for specified payload using optimal memory layout.
  • Code compatible across all BF5xx processors, with silicon anomaly workarounds implemented based on BF533 Silicon Revision 0.3 and later.
  • "Data RAM" for one instance includes Scratch, Instance/State, heap (for buffering up to 400ms of payload of 160 bytes), Minimum Input and Output Single Buffers.
  • 1 KiB = 1024 Bytes.
  • BF533, BF561, BF518 and BF561 supported.

Systems Requirements

  • Windows XP Professional SP3 (32-bit only).
  • Windows Vista Business/Enterprise/Ultimate SP2 (32-bit only). It is recommended to install the software in a non-UAC-protected location.
  • Windows 7 Professional/Enterprise/Ultimate (32 and 64-bit). It is recommended to install the software in a non-UAC-protected location.
  • Minimum of 2 GHz single core processor, 3.3 GHz dual core is recommended.
  • Minimum of 1 GB memory (RAM), 4 GB is recommended.
  • Minimum of 2 GB hard disk (HDD) space is required.

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