AN-2597: An OFDM-Based HDL Reference Modem Using the AD936x RF Transceivers

Introduction

Analog Devices, Inc., provides best-in-class RF transceiver chips, including the AD936x and ADRV900x, which have dual transmitters and receivers, as well as an RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers. These devices are designed for cellular base stations. However, these can be also utilized for unmanned aerial vehicle (UAV) and drone applications. Additionally, software enabled evaluation platforms also accompany these devices for interfacing and ease of use. Some of these software defined radio (SDR) platforms are the ADALM-PLUTO, the AD-FMCOMMS2/3/4/5 evaluation boards, and the ADRV936x system-on-module (SOM). These platforms come with free software examples including application programming interface (API) such as MATLAB, Python, C++, GNU Radio, hardware description language (HDL) intellectual properties (IPs), schematics, and production files.

However, despite the availability of evaluation platforms and APIs, some users may not be able to expand the current evaluation platforms and create their own optimal transceiver modules. To help address this, the ADSW-OFDMS2M HDL reference modem was developed to show users how to use the AD936x and the ADRV900x transceivers for wireless communication and video transmission applications.

The ADSW-OFDMS2M is implemented on the ADRV9361-Z7035 SOM, which carries the AD9361 RF transceiver and the Xilinx Zynq®-7000 all programmable (AP) system-on-chip (SoC), but may be ported to other ADI transceiver chips. The ADSW-OFDMS2M reference modem integrates an HDL physical (PHY) layer, alongside a demo application for video streaming. Table 1 summarizes the main features of the ADSW-OFDMS2M reference modem.

Application Setup

Figure 1 illustrates a typical drone system consisting of a drone and a controller device. The drone is equipped with a camera and captures the real-world data (video and telemetry). A controller device receives these video and telemetry data from the drone. In addition, the controller sends commands or instructions to manage and navigate the drone.

As proof of concept, both drone and controller devices are replaced with a field-programmable gate array (FPGA) board and a transceiver evaluation platform. The FPGA is loaded with the ADSWOFDMS2M HDL transceiver software to enable communication between the two devices. Additionally, a graphical user interface (GUI) was developed to make interfacing with the system easier. Figure 2 shows a demonstration setup using the ADRV9361 hardware.

Figure 3 shows the demo application as run from the Kuiper Linux desktop. The ADSW-OFDMS2M demo application has two operating modes which emulate functions for the drone and controller side, respectively. The drone mode is expected to start the video streaming and receive the telemetry commands. The controller mode sends telemetry commands while receiving and performing video playback.

Signal Processing Chain

The communication stack is enabled by the ADRV9361-Z7035 SOM FPGA where the baseband signal processing for the PHY layer is implemented. The baseband signal processing includes the transmitter and the receiver chains, as well as a lower media access control (MAC) layer. For the PHY layer to communicate with user space applications, it reuses the existing Linux networking stack, upper-level protocols, such as TCP/IP stack, and loadable drivers.

The HDL PHY layer is built on top of Analog Devices existingHDL libraries and an open-source Linux mac80211 compatible Wi-Fi chip design based on SDR. The PHY layer implements orthogonal frequency division multiplexing 1T1R single-input singleoutput (OFDM-SISO) mode, and is further extended to support multiple-input multiple-output (OFDM-MIMO) spatial diversity mode. Figure 4 shows the signal chain implemented in the FPGA. IQ data from the FPGA baseband processing is then passed to the AD9361 transceiver. The transceiver handles conversion from digital IQ data to RF signal, and vice versa, while sharing a common frequency synthesizer. The AD9361 also features two identical and independently controlled channels that can transmit and receive signals from different sources, making it suitable to implement a 1T1R SISO modem or a 2T2R MIMO modem.

Verification of the device is done using MATLAB WLAN Toolbox and Vivado. The verification methodology includes generating test signals from MATLAB, with different modulation and coding schemes (MCS). The lowest modulation and coding scheme (MCS) index corresponds to the setting that is least susceptible to noise and requires lower signal-to-noise ratio (SNR) for recovery. On the other hand, a higher MCS index requires higher SNR. Table 2 lists down the MCS indices, their equivalent modulation, and their coding rate.

The MATLAB WLAN toolbox wlanTGacChannel function is used to simulate a Rayleigh fading channel for both SISO and MIMO implementations. This gives a more complete simulation of the effects the channel has on the transmitted signals. Figure 5 shows the bit error rate (BER) vs. SNR curves comparing SISO and MIMO. Bit error rate on the y-axis denotes how much bit error is received vs. the SNR of the signal. The dashed lines in the figure represents results for SISO, while the solid lines are for MIMO. In general, for the same MCS index, MIMO performs better over SISO, requiring lower SNR to achieve the same BER level.

A video demonstration of this HDL reference design is available in this page: ADSW-OFDMS2M Overview.

References

AD9361 RF Agile Transceiver, Analog Devices.

ADRV9009 Integrated Dual RF Tx, Rx, and Observation Rx, Analog Devices.

Introduction to boards based on the AD9361/AD9363/AD9364, Analog Devices Wiki.

ADI HDL GitHub Repository, Analog Devices.

Jiao, Xianjun, Liu, Wei, Mehari, Michael, Aslam, Muhammad, Moerman, Ingrid. “openwifi: a free and open-source IEEE802.11 SDR implementation on SoC”, 2020 IEEE 91st Vehicular Technology Conference (VTC2020-Spring), pages 1–2, 2020.