HMCAD1050-40 Data Sheet4/22/2015
Features and Benefits
- 13-bit resolution
- 20/40 MSPS maximum sampling rate
- Ultra-Low Power Dissipation: 30/55 mW
- 72.5 dB SNR @ 8 MHz FIN
- Internal reference circuitry
- 1.8 V core supply voltage
- 1.7 - 3.6 V I/O supply voltage
- Parallel CMOS output
- Dual channel
- Pin compatible with HMCAD1040-40
- 9×9 mm QFN 64 Pin (LP9) Package
The HMCAD1050-40 is a high performance low power dual analog-to-digital converter (ADC). The ADC employs internal reference circuitry, a CMOS control interface, CMOS output data and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the complete full scale range.
Several idle modes with fast startup times exist. Each channel can be independently powered down and the entire chip can either be put in Standby Mode or Power Down mode. The different modes are optimized to allow the user to select the mode resulting in the lowest possible energy consumption during idle mode and startup.
The HMCAD1050-40 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave and CMOS clock inputs.
- Handheld Communication, PMR, SDR
- Medical Imaging
- Portable Test Equipment
- Digital Oscilloscopes
- Baseband/IF Communication
- Video Digitizing
- CCD Digitizing
Product Lifecycle Last Time Buy
All products in this family will be obsolete soon. Please contact ADI Sales or Distributors to arrange for final purchases and read our Obsolescence Information to review the time periods for placing final orders and receiving final shipments.