DS34S104
NOT RECOMMENDED FOR NEW DESIGNSSingle/Dual/Quad/Octal TDM-Over-Packet Transport Devices
Smallest, Most Robust, Lowest Cost Choice for Delivering TDM Services Over Pseudowires
- Part Models
- 1
- 1ku List Price
- price unavailable
Overview
- Transport of E1, T1, E3, T3 or STS-1 TDM or CBR Serial Signals Over Packet Networks
- Full Support for These Mapping Methods: SAToP, CESoPSN, TDMoIP (AAL1), HDLC, Unstructured, Structured, Structured with CAS
- Adaptive Clock Recovery, Common Clock, External Clock and Loopback Timing Modes
- On-Chip TDM Clock Recovery Machines, One Per Port, Independently Configurable
- Clock Recovery Algorithm Handles Network PDV, Packet Loss, Constant Delay Changes, Frequency Changes and Other Impairments
- 64 Independent Bundles/Connections
- Multiprotocol Encapsulation Supports IPv4, IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet
- VLAN Support According to 802.1p and 802.1Q
- 10/100 Ethernet MAC Supports MII/RMII/SSMII
- Selectable 32-Bit, 16-Bit or SPI Processor Bus
- Operates from Only Two Clock Signals, One for Clock Recovery and One for Packet Processing
- Glueless SDRAM Buffer Management
- Low-Power 1.8V Core, 3.3V I/O
These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial stream to be transported transparently over IP, MPLS or Ethernet networks. Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications. TDM data is transported in up to 64 individually configurable bundles. All standards-based TDM-over-packet mapping methods are supported except AAL2. Frame-based serial HDLC data flows are also supported. The high level of integration available with the DS34S10x devices minimizes cost, board space, and time to market.
Applications
- Cellular Backhaul Over PSN
- HDLC-Based Traffic Transport Over PSN
- Leased-Line Services Over PSN
- Multiservice Over Unified PSN
- TDM Circuit Extension Over PSN
- TDM Over Cable
- TDM Over GPON/EPON
- TDM Over Wireless
Documentation
Data Sheet 1
Reliability Data 1
Design Note 2
Technical Articles 2
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| DS34S104GN+ | Chip-Scale Ball-Grid Array |
This is the most up-to-date revision of the Data Sheet.
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Interface Transceivers 4 | ||
| DS34T108 | NOT RECOMMENDED FOR NEW DESIGNS | Single/Dual/Quad/Octal TDM-Over-Packet Chip |
| DS34T104 | NOT RECOMMENDED FOR NEW DESIGNS | Single/Dual/Quad/Octal TDM-Over-Packet Chip |
| DS34T102 | NOT RECOMMENDED FOR NEW DESIGNS | Single/Dual/Quad/Octal TDM-Over-Packet Chip |
| DS34T101 | Obsolete | Single/Dual/Quad/Octal TDM-Over-Packet Chip |
Tools & Simulations
BSDL Model File 1
IBIS Model 1
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