DS33R11

Ethernet Mapper with Integrated T1/E1/J1 Transceiver

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Overview

10/100 IEEE 802.3 Ethernet MAC (MII and RMII) Half/Full Duplex with Automatic Flow Control
Integrated T1/E1/J1 Framer and LIU
HDLC/LAPS Encapsulation with Programmable FCS and Interframe Fill
Committed Information Rate Controller Provides Fractional Allocations in 512kbps Increments
Programmable BERT for Serial (TDM) Interface
External 16MB, 100MHz SDRAM Buffering
Parallel Microprocessor Interface
1.8V, 3.3V Supplies
Reference Design Routes on Two Signal Layers
IEEE 1149.1 JTAG Support

The DS33R11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over a T1/E1/J1 data stream.

The device performs store-and-forward of packets with full wire-speed transport capability. The built-in Committed Information Rate (CIR) Controller provides fractional bandwidth allocation up to the line rate in increments of 512kbps. The DS33R11 can operate with an inexpensive external processor.

Applications

Ethernet Delivery Over T1/E1/J1
LAN Extension
Transparent LAN Service

Documentation

This is the most up-to-date revision of the Data Sheet.

Hardware Ecosystem

Parts	Product Life Cycle	Description
Interface Transceivers & Isolators 4
DS33Z11		Ethernet Mapper
DS33Z44		Quad Ethernet Mapper
DS33Z41		Quad IMUX Ethernet Mapper
DS2155		T1/E1/J1 Single-Chip Transceiver

Tools & Simulations

IBIS Model 1

DS33R11 IBIS Model

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Overview

Documentation

Data Sheet 1

Reliability Data 1

Technical Articles 1

Hardware Ecosystem

Tools & Simulations

IBIS Model 1

Latest Discussions

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