DS33Z44

Obsolete

Quad Ethernet Mapper

Data Sheet (Rev. 1) Product Selection Table

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Overview

Four 10/100 IEEE 802.3 Ethernet MACs (MII and RMII) Half/Full-Duplex with Automatic Flow Control
Four 52Mbps Synchronous TDM Serial Ports with Independent Transmit and Receive Timing
HDLC/LAPS Encapsulation with Programmable FCS and Interframe Fill
Committed Information Rate Controllers Provide Fractional Allocations in 512kbps Increments
Programmable BERT for Serial (TDM) Interfaces
External 16MB, 100MHz SDRAM Buffering
Parallel Microprocessor Interface
SPI Interface and Hardware Mode for Operation Without a Host Processor
1.8V Operation with 3.3V Tolerant I/O
IEEE 1149.1 JTAG Support

The DS33Z44 extends four 10/100 Ethernet LAN segments by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over four PDH/TDM data streams. The serial links support bidirectional synchronous interconnect up to 52Mbps over xDSL, T1/E1/J1, T3/E3, V.35/Optical, OC-1/EC-1, or SONET/SDH Tributary.

The device performs store-and-forward of packets with full wire-speed transport capability. The built-in Committed Information Rate (CIR) controllers provide fractional bandwidth allocation up to the line rate in increments of 512kbps. The DS33Z44 can operate with an inexpensive external processor, EEPROM or in a stand-alone hardware mode.

Applications