DS3184
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DS3184

Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU

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Industry's First Multiport, T3/E3 ATM/Packet PHYs with Built-In Line Interface Units

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file View Data Sheet (Rev.3)
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BSDL Model File ADSP-DS3184 A2 BSDL Model Download 72.91KB IBIS Model DS3184 IBIS Model Download 121.33KB
Features
  • Single (DS3181), Dual (DS3182), Triple (DS3183), or Quad (DS3184) with Integrated LIUATM/Packet PHYs for DS3, E3, and Clear-Channel 52Mbps (CC52)
  • Pin Compatible for Ease of Port Density Migration in the Same PC Board Platform
  • Each Port Independently Configurable
  • Perform Receive Clock/Data Recovery and Transmit Waveshaping
  • Jitter Attenuator can be Placed Either in the Receive or Transmit Paths
  • Interfaces to 75Ω Coaxial Cable at Lengths Up 380 Meters or 1246 Feet (DS3) or 440 Meters or 1443 Feet (E3)
  • Uses 1:2 Transformers on Both Tx and Rx
  • Universal PHYs Map ATM Cells and/or HDLC Packets into DS3 or E3 Data Streams
  • UTOPIA L2/L3 or POS-PHY™ L2/L3 or SPI-3 Interface with 8-, 16-, or 32-Bit Bus Width
  • 66MHz UTOPIA L3 and POS-PHY L3 Clock
  • 52MHz UTOPIA L2 and POS-PHY L2 Clock
  • Ports Independently Configurable for Cell or Packet Traffic in POS-PHY Bus Modes
  • Direct, PLCP, DSS, and Clear-Channel Cell Mapping
Additional Details
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The DS3181, DS3182, DS3183, and DS3184 (DS318x) integrate ATM cell/HDLC packet processor(s) with a DS3/E3 framer(s) and LIU(s) to map/demap ATM cells or packets into as many as four DS3/E3 physical copper lines with DS3-framed, E3-framed, or clear-channel data streams on per-port basis.

Applications

  • Access Concentrators
  • ATM and Frame Relay Equipment
  • Digital Cross Connect
  • Integrated Access Device (IAD)
  • Multiservice Access Platform (MSAP)
  • Multiservice Protocol Platform (MSPP)
  • PBXs
  • PDH Multiplexer/Demultiplexer
  • Routers and Switches
  • SONET/SDH ADM
  • SONET/SDH Muxes
  • Test Equipment
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file View Data Sheet (Rev.3)
Documentation View All Documentation
BSDL Model File ADSP-DS3184 A2 BSDL Model Download 72.91KB IBIS Model DS3184 IBIS Model Download 121.33KB
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DS3184

Documentation

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Data Sheet

3

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UPDATED 12/14/2006
English

DS3181-DS3184: Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU Data Sheet (Rev.3)

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UPDATED 01/01/1900
Chinese

4237: 单/双/三/四路ATM/分组PHY，内置LIU Data Sheet

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UPDATED 01/01/1900
Japanese

4237: LIU内蔵シングル/デュアル/トリプル/クワッドATM/パケットPHY Data Sheet

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3.00M
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Reliability Data

1

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UPDATED 01/12/2023
English
DS3184 Reliability Data redirect icon

11.37K

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Design Note

3

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UPDATED 12/21/2004
English
Configuration of CLAD for DS318x redirect icon

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UPDATED 04/14/2005
Chinese
DS318x中CLAD的配置 redirect icon

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UPDATED 06/27/2005
Japanese
DS318xのためのCLADの設定 redirect icon

Application Note

1

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UPDATED 12/22/2004
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Guidelines for Laying Out T3 and E3 Network Interfaces redirect icon

Technical Articles

13

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UPDATED 10/15/2001
English
T1/E1 and T3/E3 Transformer Selection Guide redirect icon

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UPDATED 06/20/2005
English
Measuring Return Loss on T3/E3/STS-1 LIUs redirect icon

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UPDATED 11/09/2005
Chinese
T3/E3/STS-1 LIU的回波损耗测量 redirect icon

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UPDATED 12/06/2005
Japanese
T3/E3/STS-1 LIU上でのリターンロスの測定 redirect icon

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UPDATED 09/23/2005
English
Clock-Rate-Adapter (CLAD) Features for DS325X, DS316X, DS317X, and DS318X redirect icon

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UPDATED 03/06/2006
Chinese
DS325X、DS316X、DS317X和DS318X中时钟速率适配器(CLAD)的使用 redirect icon

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UPDATED 02/20/2006
Japanese
DS325X、DS316X、DS317X、およびDS318Xのクロックレートアダプタ(CLAD)の機能 redirect icon

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UPDATED 12/14/2005
English
Measuring Return Loss Using the Advantest R3132 Spectrum Analyzer redirect icon

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UPDATED 12/14/2005
Chinese
利用Advantest R3132频谱分析仪测量回波损耗 redirect icon

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UPDATED 05/25/2006
Japanese
Advantest R3132スペクトルアナライザを使用したリターンロスの測定 redirect icon

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UPDATED 03/08/2006
English
Measuring and Improving Return Loss on the DS317x and DS318x T3/E3/STS-1 LIUs redirect icon

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UPDATED 08/23/2006
Chinese
DS317x与DS318x T3/E3/STS-1 LIU回波损耗的测量与改善 redirect icon

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UPDATED 07/12/2006
Japanese
DS317xおよびDS318x T3/E3/STS-1 LIUにおけるリターンロスの測定と改善 redirect icon

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