DS2156

T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Industry's First T1/E1/J1 Transceiver for ATM Applications

Data Sheet (Rev. 3)
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Overview

  • Complete T1/DS1/ISDN-PRI/J1 transceiver functionality
  • Complete E1 (CEPT) PCM-30/ISDN-PRI transceiver functionality
  • User-selectable TDM or UTOPIA II bus interface
  • Long-haul and short-haul line interface for clock/data recovery and waveshaping
  • CMI coder/decoder for optical I/F
  • Crystal-less jitter attenuator
  • Fully independent transmit and receive functionality
  • Dual HDLC controllers
  • Programmable BERT generator and detector
  • Internal software-selectable receive and transmit-side termination resistors for 75Ω/100Ω/120Ω T1 and E1 interfaces
  • Dual two-frame elastic-store slip buffers that connect to asynchronous backplanes up to 16.384MHz
  • 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz clock output synthesized to recovered network clock
  • Additional features listed in full data sheet

The DS2156 is a software-selectable T1, E1, or J1 single-chip transceiver (SCT) for short-haul and long-haul applications. The backplane is user-configurable for a TDM or UTOPIA II bus interface. The DS2156 is composed of a line interface unit (LIU), framer, HDLC controllers, and a UTOPIA/TDM backplane interface, and is controlled by an 8-bit parallel port configured for Intel or Motorola bus operations. The DS2156 is pin and software compatible with the DS2155.

The LIU is composed of transmit and receive interfaces and a jitter attenuator. The transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used. T1 waveform generation includes DSX-1 line buildouts as well as CSU line buildouts of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for both 75Ω coax and 120Ω twisted cables. The receive interface provides network termination and recovers clock and data from the network.

Applications

  • Add/Drop Multiplexers
  • Inverse Mux ATM (IMA)
  • Routers/Switches
  • T1/E1/J1 Line Cards
DS2156
T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface
DS2156, DS2156L, DS2156LN: Block Diagram
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Documentation

Data Sheet 1

Reliability Data 1

Application Note 1

Design Note 7

Technical Articles 7

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Hardware Ecosystem

Parts Product Life Cycle Description
Interface Transceivers & Isolators 4
DS21352
NOT RECOMMENDED FOR NEW DESIGNS 3.3V DS21352 and 5V DS21552 T1 Single Chip Transceivers
DS21354
NOT RECOMMENDED FOR NEW DESIGNS 3.3V/5V E1 Single Chip Transceivers (SCT)
DS21552
NOT RECOMMENDED FOR NEW DESIGNS 3.3V DS21352 and 5V DS21552 T1 Single Chip Transceivers
DS21554
NOT RECOMMENDED FOR NEW DESIGNS 3.3V/5V E1 Single Chip Transceivers (SCT)
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Tools & Simulations

BSDL Model File 2

IBIS Model 1

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