The ADSKPMB10-EV-FMCZ signal chain kit is a two-board solution, which consists of a Precision Medium Bandwidth Data Acquisition Solution on a PMOD form factor and a Fully Isolated PMOD-to-FMC interposer board.

The Precision Medium Bandwidth Data Acquisition Solution features a discrete programmable gain instrumentation amplifier (PGIA) that was built using a 30V, High Speed, Low Noise, Low Bias Current, JFET Operational Amplifier, the ADA4627-1, a Precision Quad Matched Resistor Network, the LT5400, a Low Capacitance, 4-Channel, ±15 V/+12 V iCMOS^™ Multiplexer, the ADG1209 and the internal Fully Differential Amplifier (FDA) ADC driver of the ADAQ4003. The PGIA in thru front-end offers high input impedance that allows direct interface with a variety of sensors. A programmable gain is often needed to adapt the circuit to different input signal amplitudes—unipolar or bipolar and single-ended or differential with varying common-mode voltages. The PGIA works with the ADAQ4003, an 18-Bit, 2 MSPS, µModule^® Data Acquisition Solution.

The Fully Isolated PMOD-to-FMC interposer board was designed using a Low Noise, 1A, 1MHz Push-Pull DC/DC Driver with Duty Cycle Control, the LT3999, a Robust 3.0kVrms Digital Isolators w/ Fail-Safe for the SPI lines and PGIA gain control pins, the ADuM152N and the ADuM120N, and a Low noise and ultra-low noise LDO regulators the ADP7105 and the ADP150N respectively.

APPLICATIONS

• Data acquisition and system monitoring
• Automated test equipment
• Instrumentation 
• Medical equipment

The EVAL-5CH6CHSOICEBZ supports 5-channel and 6-channel iCoupler^® standard data isolators in a 16-lead SOIC package. The evaluation board provides a JEDEC standard, 16-lead SOIC_N and SOIC_W pad layout. This layout supports signal distribution, loopback, and loads referenced to the VDDx or GNDx planes, as well as optimal bypass capacitance. Signal sources can be conducted to the evaluation board through header pins or through edge mounted SMA connectors (SMA connectors must be ordered separately). Screw terminal blocks on the evaluation board provide power connections.

The evaluation board includes 0.2 inch header positions for compatibility with active probes (probe header pins must be ordered separately).

The evaluation board follows best PCB design practices for 4-layer boards, including a full power plane and ground plane on each side of the isolation barrier. No other electromagnetic interference (EMI) or noise mitigation design features are included on the evaluation board. In cases of high speed operation, or when ultralow emissions are required, refer to the AN-1109 Application Note for additional evaluation board layout techniques.