Features and Benefits
- Dual-enhanced SHARC+ high performance floating-point cores
- Up to 500 MHz per SHARC+ core
- Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache)
- 32-bit, 40-bit, and 64-bit floating-point support
- 32-bit fixed point
- Byte, short word, word, long word addressed
- arm® Cortex-A5 core
- 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle
- 32 kB L1 instruction cache with parity/32 kB L1 data cache with parity
- 256 kB L2 cache with parity
- Powerful DMA system
- On-chip memory protection
- Integrated safety features
- 17 mm × 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP, RoHS compliant
- Low system power across automotive temperature range
- Large on-chip L2 SRAM with ECC protection, up to 1 MB
- One L3 interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.5 V capable DDR3L devices), DDR2, or LPDDR1 SDRAM devices
- Security and Protection
- Cryptographic hardware accelerators
- Fast secure boot with IP protection
- Support for arm® TrustZone
- FIR, IIR offload engines
- Qualified for automotive applications
The ADSP-SC57x/ADSP-2157x processors are members of the SHARC® family of products. The ADSP-SC57x processor is based on the SHARC+® dual-core and the arm® Cortex®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.
By integrating a set of industry leading system peripherals and memory, the arm® Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.
Markets and Technologies
Product Lifecycle Production
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
Evaluation Kits (2)
The Analog Devices ICE-1000 and ICE-2000 emulators facilitate the creation, test, and debug of advanced applications on Analog Devices Processors and DSPs. Working in tandem with the CrossCore® Embedded Studio development environment, these emulators provide state-of-the-art support for all JTAG-compliant Analog Devices processors.
New debug feature added for the ICE-1000/ICE-2000:
- Coresight Serial Wire Debug (SWD)
Features & Benefits
- JTAG/SWD support for Blackfin, Blackfin+, SHARC and multi-core SHARC+ with ARM
- Plug-n-Play, USB 2.0 compliant
- USB bus-powered device
- Windows® 8.1, Window 7 compatible
- Multiple processor I/O voltage support: 1.8V, 2.5V, and 3.3V
- Multiprocessor support
- JTAG/SWD clock operation of 5 MHz on the ICE-1000
- JTAG/SWD clock operation up to 46 MHZ on the ICE-2000
- Multi-colored LED for enhanced status indication
- Software controlled target reset to support remote debug
The ADSP-SC573 processor is a member of the SHARC® family of products. The ADSP-SC573 processor is based on the SHARC+ dual-core and the arm® Cortex-A5TM core. The ADSP-SC573 SHARC processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices Super Harvard Architecture. These 32-bit/40- bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with their large onchip SRAM, multiple internal buses to eliminate I/O bottlenecks, and innovative digital audio interfaces (DAI). New enhancements to the SHARC+ core add cache enhancements, branch prediction, and other instruction set improvements—all while maintaining instruction set compatibility to previous SHARC products. The EZ-KIT ships with all of the necessary hardware to get you up and running and start the evaluation immediately
Features & Benefits
- ADSP-SC573 400-pin 17x17mm BGA
- 2Gb DDR3 Memory
- 128 Mb SPI Flash
- 2 x Ethernet (1x 10/100, 1x GigE)
- ADAU1979 quad ADC
- ADAU1962A 12 channel 24-bit DAC
- ADAU1977 quad ADC with diagnostics
- SPDIF in/out, optical & coax
- 2 CAN transceivers + RJ11 connectors
- USB OTG
- SD/MMC memory connector
- EI3 Expansion Interface
- CrossCore® Embedded Studio EZ-KIT license and ICE-1000 emulator
Documentation & Resources
EE-428: Tips and Tricks Using the ADSP-SC57x/ADSP-2157x Processor Boot ROM11/16/2020
EE-401: ADSP-SC5xx/215xx SHARC+ Processor System Optimization Techniques (Rev. 1)2/9/2018
EE-399: The Linux Run-Time SHARC Loader on ADSP-SC57x/SC58x Processors (Rev. 3)11/8/2017
EE-400: Using Cache on ADSP-SC5xx/ADSP-215xx SHARC+ Processors (Rev. 1)9/25/2017
EE-397: Estimating Power for ADSP-SC57x/ADSP-2157x SHARC+® Processors (Rev. 1 - July 20, 2017)7/21/2017
EE-387: Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/ADSP-215xx Processors (Rev. 3)1/8/2016
EE-253: Power Bypass Decoupling of SHARC® Processors (Rev. 1)12/5/2006
EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev. 1)2/15/2005
Software & Systems Requirements
Operating Systems and Middleware
Software Development Tools
Tools & Simulations
BSDL Model Files
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Support & Discussions
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.