Overview
Features and Benefits
- Glueless Clusters of up to six SHARCs
- Link Ports for 2D & 3D Arrays
- Distributed Bus Arbitration
- Unified Memory Space
- Link Ports Provide Up To 80MB/sec I/O Each
- 320 MB/sec External Port
- Hardware Support for Semaphores
Product Details
The ADSP-21160M DSP is a SHARC processor that is optimized for applications such as telephony, medical imaging, radar/sonar electronics, communications, 3D graphics and imaging. The ADSP-21160M features a Single-Instruction-Multiple-Data (SIMD) architecture.
Using two computational units (ALU, Barrel Shifter, MAC, Register files), the ADSP-21160M can have a five fold performance increase versus the ADSP-2106x on a range of DSP algorithms. It is code compatible with ADI's popular first generation ADSP-2106x SHARC DSPs. Like other SHARCs, the ADSP-21160M is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21160M includes an 80 MHz core for processing both 32-bit fixed-point and (32-bit, 40-bit) floating-point data types, a dual-ported 4 Mbit on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal busses to eliminate I/O bottlenecks.
The ADSP-21160M is optimized for multiprocessing topologies; SHARC supports multiprocessing via link ports or an external port. In the diagram below, both cluster and link port multiprocessing is shown. Over the external port up to six 21160Ms may be connected together without any additional support logic. The arbitration for this shared bus is integrated on-chip. Each SHARC in the cluster has access to every SHARC's internal memory. Through the external port connection, optional external memory may be shared as well.
The six link ports are another way to gluelessly connect a multiprocessing system. Both, the links and the cluster can be used simultaneously and systems with hundreds of SHARC DSPs can be developed using both peripherals.
Maximize Speed, Minimize Size
The ADSP-21160M is offered in a 27mm x 27mm 400-ball PBGA (Plastic Ball Grid Array) package 40% smaller than processors in this performance class.
More Processing Per Watt
In addition to small size and high performance, the 21160M's power dissipation enables new levels of MFLOPS per watt. The ADSP-21160M typical power dissipation is 2 watts, enabling 240 MFLOPS of performance per watt. This allows designers to use multiple processors on a PCI card within the PCI power limit of 25 watts. With eight 21160M DSPs, providing 480 MFLOPS each, a standard PCI card design can obtain 3.84 GFLOPS performance and leave 9 watts for other circuitry.
The ADSP-21160M is supported by hundreds of readily available third-party hardware and software products and ADI's powerful VisualDSP++ development system, allowing for fast and easy development, debug and deployment.
Product Categories
Product Lifecycle
Production
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
Evaluation Kits (1)
Documentation & Resources
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EE-112: Class Implementation in Analog C++11/14/2016
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EE-356: Emulator and Evaluation Hardware Troubleshooting Guide for CCES Users (Rev. 2)2/14/2015
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• EE-356: Associated Files
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EE-332: Cycle Counting and Profiling (Rev. 2)8/18/2009
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• EE-332: Code example
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EE-340: Connecting SHARC® and Blackfin® Processors over SPI (Rev. 1)5/8/2009
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• EE-340: Code example
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EE-323: Implementing Dynamically Loaded Software Modules (Rev. 1)3/8/2008
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• EE-323: Associated Code
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EE-330: Windows Vista Compatibility in VisualDSP++ 5.0 Development Tools (Rev. 1)8/31/2007
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EE-328: Migrating from ADSP-2106x/2116x to ADSP-2126x/2136x/2137x SHARC® Processors (Rev. 1)7/27/2007
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EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev. 14)5/21/2007
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• EE-175: Associated Files
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EE-56: Tips and Tricks on SHARC® EPROM and Host Boot Loader (Rev. 3)3/7/2007
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EE-84: External Port DMA Modes of Operation for SHARC Processors (Rev. 2)3/2/2007
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• EE-84: Code Example (Rev 2, 2/2007)
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EE-223: In-Circuit Flash Programming on SHARC® Processors (Rev. 2)2/23/2007
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• EE-223: Code Example (Rev 2, 02/2007)
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EE-253: Power Bypass Decoupling of SHARC® Processors (Rev. 1)12/5/2006
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EE-305: Designing and Debugging Systems with SHARC Processors (Rev. 1)11/15/2006
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EE-284: Implementing Overlays on ADSP-21160 SHARC® Processors (Rev. 1)3/20/2006
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• EE-284: Software Code
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EE-270: Extended-Precision Fixed-Point Arithmetic on SIMD SHARC® Processors (Rev. 1)7/8/2005
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• EE-270 Software Code
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EE-267: Implementing In-Place FFTs on SISD and SIMD SHARC® Processors (Rev. 1)4/4/2005
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• EE-267 Software Code
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EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev. 1)2/15/2005
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EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev. 3)9/15/2004
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• EE-202 Software Code
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EE-241: SHARC® DSPs to TigerSHARC® Processors Code Porting Guide (Rev. 1)7/19/2004
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• EE-241 Software Code
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EE-195: Moving from the ADSP-21160M SHARC® DSP to the ADSP-21160N SHARC DSP9/10/2003
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EE-191: Implementing a Glueless UART Using The SHARC® DSP SPORTs5/21/2003
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• EE-191 Software Code
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EE-177: SHARC® SPI Slave Booting (Rev. 3)5/2/2003
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• EE-177: Code Example (Rev 3, 01/2007)
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EE-68: Analog Devices JTAG Emulation Technical Reference (Rev. 10)12/20/2002
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EE-141: Benchmarking C Code on the ADSP-2106x and the ADSP-2116x Family of DSPs12/16/2002
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EE-148: Introduction to SHARC® Multiprocessor Systems using VisualDSP++™9/26/2002
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• EE-148 Software Code
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EE-160: Examining ADSP-21160 Link Port Backward Compatibility to the ADSP-2106x Link Ports9/18/2002
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• EE-160 Software Code
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EE-140: Using the ADSP-21160 Serial Ports in Multi-channel Mode9/18/2002
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EE-134: Writing C Compatible Assembly Code Interrupt Handlers for the SHARC® Family9/18/2002
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EE-132: Placing C Code and Data Modules in SHARC memory using VisualDSP++™9/18/2002
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• EE-132 Software Code
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EE-128: DSP in C++: Calling Assembly Class Member Functions From C++9/18/2002
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EE-106: Link Port Open Systems Interconnect Cable Standard9/17/2002
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EE-77: SHARC Link Port Booting9/17/2002
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EE-69: Understanding and Using Linker Description Files on SHARC Processors (Rev. 2)9/17/2002
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• EE-69: Code Example (Rev 2, 01/2007)
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EE-110: A Quick Primer on ELF and DWARF File Formats5/17/2000
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EE-104: Setting Up Streams with the VisualDSP Debugger11/5/1999
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• EE-104 Software Code
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SHARC Processor Family9/21/2010
Software & Systems Requirements
Software & Tools Anomaly
Tools & Simulations
Design Tool
BSDL Model File
Designing with BGA
Surface Mount Assembly Recommendations for Plastic Ball Grid Array (PBGA) Packages
Design Resources
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
| Part Number | Material Declaration | Reliability Data | Pin/Package Drawing | CAD Symbols, Footprints & 3D Models |
|---|---|---|---|---|
| ADSP-21160MKBZ-80 | Material Declaration | Reliability Data | 400-Ball PBGA (27mm x 27mm) | |
| Wafer Fabrication Data |
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