Features and Benefits
- Glueless Clusters of up to six SHARCs
- Link Ports for 2D & 3D Arrays
- Distributed Bus Arbitration
- Unified Memory Space
- Link Ports Provide Up To 80MB/sec I/O Each
- 320 MB/sec External Port
- Hardware Support for Semaphores
The ADSP-21160M DSP is a SHARC processor that is optimized for applications such as telephony, medical imaging, radar/sonar electronics, communications, 3D graphics and imaging. The ADSP-21160M features a Single-Instruction-Multiple-Data (SIMD) architecture.
Using two computational units (ALU, Barrel Shifter, MAC, Register files), the ADSP-21160M can have a five fold performance increase versus the ADSP-2106x on a range of DSP algorithms. It is code compatible with ADI's popular first generation ADSP-2106x SHARC DSPs. Like other SHARCs, the ADSP-21160M is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21160M includes an 80 MHz core for processing both 32-bit fixed-point and (32-bit, 40-bit) floating-point data types, a dual-ported 4 Mbit on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal busses to eliminate I/O bottlenecks.
The ADSP-21160M is optimized for multiprocessing topologies; SHARC supports multiprocessing via link ports or an external port. In the diagram below, both cluster and link port multiprocessing is shown. Over the external port up to six 21160Ms may be connected together without any additional support logic. The arbitration for this shared bus is integrated on-chip. Each SHARC in the cluster has access to every SHARC's internal memory. Through the external port connection, optional external memory may be shared as well.
The six link ports are another way to gluelessly connect a multiprocessing system. Both, the links and the cluster can be used simultaneously and systems with hundreds of SHARC DSPs can be developed using both peripherals.
Maximize Speed, Minimize Size
The ADSP-21160M is offered in a 27mm x 27mm 400-ball PBGA (Plastic Ball Grid Array) package 40% smaller than processors in this performance class.
More Processing Per Watt
In addition to small size and high performance, the 21160M's power dissipation enables new levels of MFLOPS per watt. The ADSP-21160M typical power dissipation is 2 watts, enabling 240 MFLOPS of performance per watt. This allows designers to use multiple processors on a PCI card within the PCI power limit of 25 watts. With eight 21160M DSPs, providing 480 MFLOPS each, a standard PCI card design can obtain 3.84 GFLOPS performance and leave 9 watts for other circuitry.
The ADSP-21160M is supported by hundreds of readily available third-party hardware and software products and ADI's powerful VisualDSP++ development system, allowing for fast and easy development, debug and deployment.
Product Lifecycle Production
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
Evaluation Kits (1)
EMULATOR-USB & HP USB ICE
Analog Devices’ cost-effective Universal Serial Bus (USB)-based emulator and High performance (HP) Universal Serial Bus (USB)-based emulator each provide an easy, portable, non-intrusive, target-based debugging solution for Analog Devices JTAG processors and DSPs. These powerful USB-based emulators perform a wide range of emulation functions, including single-step and full speed execution with pre-defined breakpoints, and viewing and/or altering of register and memory contents. With the ability to automatically detect and support multiple I/O voltages, the USB and HP USB emulators enable users to communicate with all of the Analog Devices JTAG processors and DSPs using either a full speed USB 1.1 or high speed USB 2.0 port on the host PC. Applications and data can easily and rapidly be tested and transferred between the emulators and the separately available VisualDSP++ development and debugging environment(sold separately).
The plug-and-play architecture of USB allows the emulators to be automatically detected and configured by the host operating system. It can also be connected to and disconnected from the host without opening the PC or turning off the power to the PC. A 3-meter cable is included to connect the emulators to the host PC, thus providing abundant accessibility to hard to reach targets.
The HP USB-based emulator also supports the Background
Telemetry Channel (BTC), a non-intrusive method
for exchanging data between the host and target
application without affecting the target system's
Part Number: ADZS-USB-ICE
High Performance USB-Based Emulator
Part Number: ADZS-HPUSB-ICE
Tel: 1-800-ANALOGD (262-5643)
For additional information, contact your local Analog Devices Sales Office or Distributor.
Features & Benefits
- Full speed USB 1.1 interface enabling download speeds of up to 150 KB/Sec (ADZS-USB-ICE) or High speed USB 2.0 interface enabling download speeds of up to 1.5MB/sec (ADZS-HPUSB-ICE)
- Background Telemetry Channel (BTC) support enabling non-intrusive data exchange at up to 2.0 MB/sec (ADZS-HPUSB-ICE only)
- 1.8V, 2.5V, and 3.3V compliant and tolerant
- Support for all ADI JTAG processors and DSPs
- 5V tolerant and 3.3V compliant for 5V processors and DSPs
- Multiprocessor support
- 14-pin JTAG connector
- 3-meter USB cable for difficult-to-reach targets
Documentation & Resources
EE-112: Class Implementation in Analog C++11/14/2016
EE-356: Emulator and Evaluation Hardware Troubleshooting Guide for CCES Users (Rev. 2)2/14/2015
• EE-356: Associated Files
EE-332: Cycle Counting and Profiling (Rev. 2)8/18/2009
• EE-332: Code example
EE-340: Connecting SHARC® and Blackfin® Processors over SPI (Rev. 1)5/8/2009
• EE-340: Code example
EE-323: Implementing Dynamically Loaded Software Modules (Rev. 1)3/8/2008
• EE-323: Associated Code
EE-330: Windows Vista Compatibility in VisualDSP++ 5.0 Development Tools (Rev. 1)8/31/2007
EE-328: Migrating from ADSP-2106x/2116x to ADSP-2126x/2136x/2137x SHARC® Processors (Rev. 1)7/27/2007
EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev. 14)5/21/2007
• EE-175: Associated Files
EE-56: Tips and Tricks on SHARC® EPROM and Host Boot Loader (Rev. 3)3/7/2007
EE-84: External Port DMA Modes of Operation for SHARC Processors (Rev. 2)3/2/2007
• EE-84: Code Example (Rev 2, 2/2007)
EE-223: In-Circuit Flash Programming on SHARC® Processors (Rev. 2)2/23/2007
• EE-223: Code Example (Rev 2, 02/2007)
EE-253: Power Bypass Decoupling of SHARC® Processors (Rev. 1)12/5/2006
EE-305: Designing and Debugging Systems with SHARC Processors (Rev. 1)11/15/2006
EE-284: Implementing Overlays on ADSP-21160 SHARC® Processors (Rev. 1)3/20/2006
• EE-284: Software Code
EE-270: Extended-Precision Fixed-Point Arithmetic on SIMD SHARC® Processors (Rev. 1)7/8/2005
• EE-270 Software Code
EE-267: Implementing In-Place FFTs on SISD and SIMD SHARC® Processors (Rev. 1)4/4/2005
• EE-267 Software Code
EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev. 1)2/15/2005
EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev. 3)9/15/2004
• EE-202 Software Code
EE-241: SHARC® DSPs to TigerSHARC® Processors Code Porting Guide (Rev. 1)7/19/2004
• EE-241 Software Code
EE-195: Moving from the ADSP-21160M SHARC® DSP to the ADSP-21160N SHARC DSP9/10/2003
EE-191: Implementing a Glueless UART Using The SHARC® DSP SPORTs5/21/2003
• EE-191 Software Code
EE-177: SHARC® SPI Slave Booting (Rev. 3)5/2/2003
• EE-177: Code Example (Rev 3, 01/2007)
EE-68: Analog Devices JTAG Emulation Technical Reference (Rev. 10)12/20/2002
EE-141: Benchmarking C Code on the ADSP-2106x and the ADSP-2116x Family of DSPs12/16/2002
EE-148: Introduction to SHARC® Multiprocessor Systems using VisualDSP++™9/26/2002
• EE-148 Software Code
EE-160: Examining ADSP-21160 Link Port Backward Compatibility to the ADSP-2106x Link Ports9/18/2002
• EE-160 Software Code
EE-140: Using the ADSP-21160 Serial Ports in Multi-channel Mode9/18/2002
EE-134: Writing C Compatible Assembly Code Interrupt Handlers for the SHARC® Family9/18/2002
EE-132: Placing C Code and Data Modules in SHARC memory using VisualDSP++™9/18/2002
• EE-132 Software Code
EE-128: DSP in C++: Calling Assembly Class Member Functions From C++9/18/2002
EE-106: Link Port Open Systems Interconnect Cable Standard9/17/2002
EE-77: SHARC Link Port Booting9/17/2002
EE-69: Understanding and Using Linker Description Files on SHARC Processors (Rev. 2)9/17/2002
• EE-69: Code Example (Rev 2, 01/2007)
EE-110: A Quick Primer on ELF and DWARF File Formats5/17/2000
EE-104: Setting Up Streams with the VisualDSP Debugger11/5/1999
• EE-104 Software Code
SHARC Processor Family9/21/2010
Software & Systems Requirements
Software & Tools Anomaly
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
|Part Number||Material Declaration||Reliability Data||Pin/Package Drawing||CAD Symbols, Footprints & 3D Models|
|ADSP-21160MKBZ-80||Material Declaration||Reliability Data||400-Ball PBGA (27mm x 27mm)|
|Wafer Fabrication Data|
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