ADSP-21061L
SHARC, 44MHz, 150 MFLOPS, 3.3v, floating point
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Overview
Features and Benefits
- 50MHz (20ns instruction rate) SISD SHARC Core
- 150MFLOPs peak performance
- Code compatible with all SHARC processors
- Supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math
- 1Mbit of on-chip dual-ported SRAM
- Glueless connection for scalable DSP multiprocessing
- Two synchronous serial ports with independent transmit and receive functions
- 6 Channel DMA controller
- Host Processor Interface
Product Details
The ADSP-21061L is the newest member of the powerful SHARC® family of floating point processors. The SHARC® are signal processing microcomputers that offer new capabilities and levels of integration and performance. The ADSP-21061L is the low power (3.3 volt) version of the ADSP-21061. The ADSP-21061L is a 32-bit processor optimized for high performance DSP applications. The ADSP-21061L combines the ADSP-21000 DSP core with a dual-ported on-chip SRAM and an I/O processor with a dedicated I/O bus to form a complete system-in-a-chip.
Fabricated in a high-speed, low-power CMOS process, the ADSP-21061L has a 25 ns instruction cycle time operating at 40 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle.
The ADSP-21061L SHARC combines a high-performance floating-point DSP core with integrated, on-chip system features, including a 1 Mbit SRAM memory, host processor interface, DMA controller, serial ports and parallel bus connectivity for glueless DSP multiprocessing.
Product Categories
Product Lifecycle
Not Recommended for New Designs
This designates products ADI does not recommend broadly for new designs.
Documentation & Resources
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EE-112: Class Implementation in Analog C++11/14/2016
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EE-332: Cycle Counting and Profiling (Rev. 2)8/18/2009
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• EE-332: Code example
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EE-340: Connecting SHARC® and Blackfin® Processors over SPI (Rev. 1)5/8/2009
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• EE-340: Code example
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EE-323: Implementing Dynamically Loaded Software Modules (Rev. 1)3/8/2008
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• EE-323: Associated Code
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EE-330: Windows Vista Compatibility in VisualDSP++ 5.0 Development Tools (Rev. 1)8/31/2007
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EE-328: Migrating from ADSP-2106x/2116x to ADSP-2126x/2136x/2137x SHARC® Processors (Rev. 1)7/27/2007
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EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev. 14)5/21/2007
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• EE-175: Associated Files
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EE-280: In-Circuit Flash Programming on ADSP-2106x SHARC® Processors (Rev. 2)4/10/2007
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• EE-280: Code Example (Rev 2, 03/2007)
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EE-56: Tips and Tricks on SHARC® EPROM and Host Boot Loader (Rev. 3)3/7/2007
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EE-84: External Port DMA Modes of Operation for SHARC Processors (Rev. 2)3/2/2007
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• EE-84: Code Example (Rev 2, 2/2007)
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EE-253: Power Bypass Decoupling of SHARC® Processors (Rev. 1)12/5/2006
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EE-305: Designing and Debugging Systems with SHARC Processors (Rev. 1)11/15/2006
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EE-267: Implementing In-Place FFTs on SISD and SIMD SHARC® Processors (Rev. 1)4/4/2005
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• EE-267 Software Code
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EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev. 1)2/15/2005
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EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev. 3)9/15/2004
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• EE-202 Software Code
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EE-241: SHARC® DSPs to TigerSHARC® Processors Code Porting Guide (Rev. 1)7/19/2004
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• EE-241 Software Code
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EE-191: Implementing a Glueless UART Using The SHARC® DSP SPORTs5/21/2003
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• EE-191 Software Code
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EE-68: Analog Devices JTAG Emulation Technical Reference (Rev. 10)12/20/2002
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EE-141: Benchmarking C Code on the ADSP-2106x and the ADSP-2116x Family of DSPs12/16/2002
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EE-166: ADSP-2106x EPROM Overlay Support with VisualDSP++ 2.09/26/2002
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• EE-166 Software Code
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EE-132: Placing C Code and Data Modules in SHARC memory using VisualDSP++™9/18/2002
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• EE-132 Software Code
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EE-128: DSP in C++: Calling Assembly Class Member Functions From C++9/18/2002
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EE-116: SHARC Shortword DMA9/18/2002
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• EE-116 Software Code
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EE-109: ADSP2106x : Using 2106x SPORT's as Timers9/17/2002
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EE-86: Interfacing SHARC 2106x DSPs to PLX 9080 PCI Bridge Chips9/17/2002
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EE-85: Recommended Handling of Unused SHARC Pins9/17/2002
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EE-70: ADSP-2106x SPORT DTx pins: Is There Potential MCM Data Contention Between Different SHARCs9/17/2002
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EE-69: Understanding and Using Linker Description Files on SHARC Processors (Rev. 2)9/17/2002
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• EE-69: Code Example (Rev 2, 01/2007)
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EE-62: Accessing Short Word Memory In C9/16/2002
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EE-47: ADSP-2106x Link Ports - Maximum Throughput9/16/2002
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EE-46: SHARC Internal Power Measurements9/16/2002
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EE-45: Using the ADSP-2106x/21020 EZ-ICE DBWIN Utility9/16/2002
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EE-42: C-Programs on the ADSP-2106x9/16/2002
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EE-110: A Quick Primer on ELF and DWARF File Formats5/17/2000
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EE-104: Setting Up Streams with the VisualDSP Debugger11/5/1999
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• EE-104 Software Code
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EE-74: Analog Devices Serial Port Development and Troubleshooting Guide11/4/1999
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EE-103: Performing Level Conversion Between 5v and 3.3v IC's11/4/1999
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EE-37: How to Interface an LCD to the 21xx and 2106x Family DSP's9/21/1997
Software & Systems Requirements
Software & Tools Anomaly
Tools & Simulations
IBIS Model
BSDL Model File
Designing with BGA
Surface Mount Assembly Recommendations for Plastic Ball Grid Array (PBGA) Packages
Design Resources
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
| Part Number | Material Declaration | Reliability Data | Pin/Package Drawing | CAD Symbols, Footprints & 3D Models |
|---|---|---|---|---|
| ADSP-21061LASZ-176 | Material Declaration | Reliability Data | 240-Lead MQFP | |
| ADSP-21061LKBZ-160 | Material Declaration | Reliability Data | 225-Ball PBGA (23mm x 20mm) | |
| ADSP-21061LKSZ-160 | Material Declaration | Reliability Data | 240-Lead MQFP | |
| Wafer Fabrication Data |
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