ADM1184
Info: : PRODUCTION
searchIcon
cartIcon

ADM1184

0.8% Accurate Quad Voltage Monitor

Show More showmore-icon

Info: : PRODUCTION tooltip
Info: : PRODUCTION tooltip
Part Details
Part Models 2
1ku List Price Starting From $2.16
Features
  • Powered from 2.7 V to 5.5 V on the VCC pin
  • 4 inputs can be programmed to monitor different voltage levels with external resistor dividers
  • 3 open-drain enable outputs (OUT1, OUT2, and OUT3)
  • 10-lead MSOP
  • Open-drain power-good output (PWRGD)
  • Internal 190 ms delay associated with assertion of PWRGD
  • Monitors 4 supplies via 0.8% accurate comparators
Additional Details
show more Icon

The ADM1184 is an integrated, 4-channel voltage-monitoring device. A 2.7 V to 5.5 V power supply is required on the VCC pin to power the device.

Four precision comparators monitor four voltage rails. Each comparator has a 0.6 V reference with a worst-case accuracy of 0.8%. Resistor networks that are external to the VIN1, VIN2, VIN3, and VIN4 pins set the trip points for the monitored supply rails.

The ADM1184 has four open-drain outputs. Of these outputs, OUT1 to OUT3 can be used to enable power supplies, and PWRGD is a common power-good output indicating that all monitored supplies are above their respective thresholds.

OUT1 to OUT3 are dependent on their associated VINx input (that is, VIN1, VIN2, or VIN3). If a supply monitored by VINx drops below its programmed threshold, the associated OUTx pin and PWRGD are disabled.

PWRGD is a common power-good output indicating the status of all monitored supplies. There is an internal 190 ms (typical) delay associated with the assertion of the PWRGD output. If VIN1, VIN2, VIN3, or VIN4 drops below its programmed threshold, PWRGD is deasserted immediately.

The ADM1184 is available in a 10-lead mini small outline package (MSOP).

APPLICATIONS

  • Monitor and alarm functions
  • Telecommunications
  • Microprocessor systems
  • PC/servers
Part Models 2
1ku List Price Starting From $2.16

close icon
Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
ADM1184ARMZ
  • HTML
  • HTML
ADM1184ARMZ-REEL7
  • HTML
  • HTML

Filter by Model

reset

Reset Filters

Part Models

Product Lifecycle

PCN

Oct 26, 2015

- 15_0176

Assembly Transfer of Select 8/10L MSOP Products to Amkor Philippines

Filter by Model

reset

Reset Filters

Part Models

Product Lifecycle

PCN

Oct 26, 2015

- 15_0176

arrow down

Assembly Transfer of Select 8/10L MSOP Products to Amkor Philippines

Software & Part Ecosystem

Software & Part Ecosystem

Evaluation Kit

Evaluation Kits 2

EVAL-ADM1184

ADM1184 Evaluation Board

reference details image

AD-FMCOMMS11-EBZ

Direct RF to Baseband Transmit Radio

zoom

AD-FMCOMMS11-EBZ

Direct RF to Baseband Transmit Radio

Direct RF to Baseband Transmit Radio

Features and Benefits

  • TX
    • 16-bit 12GSPS RFDAC
    • JESD204B Interface
      • 8 lanes up to 12.5Gbps
    • 1x/2x/4x/6x/8x/12x/16x/24x/32x Interpolation
    • 64-bit NCO at max rate
    • Analog Modes of Operation:
      • Normal Mode: 6GSPS DAC rate
        • Synthesis up to 2.5GHz (1st Nyquist)
      • Mix Mode: 6GSPS DAC rate
        • Synthesis in 2nd & 3rd Nyquist zones
      • 2X Normal Mode: 12GSPS DAC rate
        • Synthesis up to 6GHz (1st Nyquist)
      • Excellent dynamic performance
  • RX
    • 3.2GHz full power bandwidth at 2.5GSPS
      • Noise Density = -149.5dBFs/Hz, ENOB = 9.5 bits
      • SFDR = 77 dBc at 1GHz Ain (2.5Gsps)
      • SFDR = 77dBc at 1.8GHz Ain (2.5Gsps)
    • +/-0.3 LSB DNL, +/-1.0 LSB INL
    • Dual supplies : 1.3V and 2.5V
    • 8 or 6 Lane JESD204B Outputs
    • Programmable clipping threshold for Fast Detect output
    • Two Integrated wide band digital down converters (DDC) per channel
      • 10-bit complex NCO
      • 2 cascaded half band filters (dec/8, dec/16)
    • Timestamp for synchronous processing alignment
      • SYSREF Setup/Hold detector
    • Programmable Interrupt (IRQ) event monitor

Product Detail

The AD-FMComms11-EBZ board is a system platform board for communication infrastructure applications that demonstrates the Direct to RF (DRF) transmitter and observation receiver architecture. Using high sample rate RFDAC(s) and RFADC(s), a number of components in previous generation transmitters can be eliminated, such as mixers, modulators, IF amplifiers and filters. The objective being to bring the ADC or DAC as close to the antenna as possible, leading to possibly more cost effective and efficient communications solution.

It is composed of multi-GSPS RF ADC and DAC, AD9625 and AD9162 respectively. The transmit path contains a balun, low pass filter, gain block and variable attenuation to produce an output appropriate for a power amplifier module. Along the observation path, the PA output is coupled back into the board through a variable attenuator, a balun and finally the ADC. Clock management is taken care of on board; all the necessary clocks are generated from a reference. Power management is present as well.

Recently Viewed