ADCLK854

RECOMMENDED FOR NEW DESIGNS

1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer

Data Sheet (Rev. A) Product Selection Table
Viewing:

Overview

  • 2 selectable differential inputs
  • Selectable LVDS/CMOS outputs
  • Up to 12 LVDS (1.2 GHz) or 24 CMOS (250 MHz) outputs
  • <12 mW per channel (100 MHz operation)
  • 54 fs rms integrated jitter (12 kHz to 20 MHz)
  • 100 fs rms additive broadband jitter
  • 2.0 ns propagation delay (LVDS)
  • 135 ps output rise/fall (LVDS)
  • 70 ps output-to-output skew (LVDS)
  • Sleep mode
  • Pin programmable control
  • 1.8 V power supply

The ADCLK854 is a 1.2 GHz/250 MHz LVDS/CMOS fanout buffer optimized for low jitter and low power operation. Possible configurations range from 12 LVDS to 24 CMOS outputs, including combinations of LVDS and CMOS outputs. Three control lines are used to determine whether fixed blocks of outputs (three banks of four) are LVDS or CMOS outputs.

The ADCLK854 offers two selectable inputs and a sleep mode feature. The IN_SEL pin state determines which input is fanned out to all the outputs. The SLEEP pin enables a sleep mode to power down the device.

The inputs accept various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS. Table 8 provides interface options for each type of connection.

This device is available in a 48-pin LFCSP package. It is specified for operation over the standard industrial temperature range of −40°C to +85°C.

APPLICATIONS

  • Low jitter clock distribution
  • Clock and data signal restoration
  • Level translation
  • Wireless communications
  • Wired communications
  • Medical and industrial imaging
  • ATE and high performance instrumentation
ADCLK854
1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer
ADCLK854-FBL ADCLK854 Pin Configuration
Add to myAnalog

Add product to the Products section of myAnalog (to receive notifications), to an existing project or to a new project.

Create New Project
Ask a Question

Documentation

Data Sheet 1

User Guide 1

Application Note 1

Technical Articles 3

Frequently Asked Question 1

Learn More
Add to myAnalog

Add media to the Resources section of myAnalog, to an existing project or to a new project.

Create New Project

Tools & Simulations

ADIsimCLK Design and Evaluation Software

ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.

Open Tool

ADCLK854 IBIS Models 2

Evaluation Kits

EVAL-ADCLK854

ADCLK854 Evaluation Board

Buy Now View Details

Product Details

The ADCLK854 data sheet contains full technical details about the specifications and operation of this device and should be consulted when using the evaluation board.

The ADCLK854 is a high performance clock fanout buffer. The evaluation board is fabricated using a high quality Rogers® dielectric material. Transmission line paths are kept as close to 100 Ω differentially as possible.
EVAL-ADCLK854
ADCLK854 Evaluation Board

Latest Discussions

46 Weeks Ago
ADCLK854 Clock puls missing
1 Years Ago
Regarding the ADCLK854 single ended clock input
2 Years Ago
Keyword Interceptor Update
View related discussion on EngineerZone®

Recently Viewed