Features and Benefits
- Low cost 3.3 V CMOS MxFE™ for broadband modems
- 10-bit D/A converter
- 2×/4× interpolation filter
- 200 MSPS DAC update rate
- Integrated 23 dBm line driver with 19.5 dB gain control
- 10-bit, 80 MSPS A/D converter
- −12 dB to +48 dB low noise RxPGA (< 3.0 nV/rtHz)
- Third order, programmable low-pass filter
- Flexible digital data path interface
- Half- and full-duplex operation
- Backward-compatible with AD9975 and AD9875
- Various power-down/reduction modes
- Internal clock multiplier (PLL)
- 2 auxiliary programmable clock outputs
- Available in 64-lead chip scale package or bare die
The AD9865 is a mixed-signal front end (MxFE) IC for transceiver applications requiring Tx and Rx path functionality with data rates up to 80 MSPS. Its flexible digital interface, power saving modes, and high Tx-to-Rx isolation make it well suited for half- and full-duplex applications. The digital interface is extremely flexible allowing simple interfaces to digital back ends that support half- or full-duplex data transfers, thus often allowing the AD9865 to replace discrete ADC and DAC solutions. Power saving modes include the ability to reduce power consumption of individual functional blocks, or to power down unused blocks in half-duplex applications. A serial port interface (SPI®) allows software programming of the various functional blocks. An on-chip PLL clock multiplier and synthesizer provide all the required internal clocks, as well as two external clocks from a single crystal or clock source.
The Tx signal path consists of a bypassable 2×/4× low-pass interpolation filter, a 10-bit TxDAC, and a line driver. The transmit path signal bandwidth can be as high as 34 MHz at an input data rate of 80 MSPS. The TxDAC provides differential current outputs that can be steered directly to an external load or to an internal low distortion current amplifier. The current amplifier (IAMP) can be configured as a current- or voltage-mode line driver (with two external npn transistors) capable of delivering in excess of 23 dBm peak signal power. Tx power can be digitally controlled over a 19.5 dB range in 0.5 dB steps.
The receive path consists of a programmable amplifier (RxPGA), a tunable low-pass filter (LPF), and a 10-bit ADC. The low noise RxPGA has a programmable gain range of −12 dB to +48 dB in 1 dB steps. Its input referred noise is less than 3 nV/rtHz for gain settings beyond 36 dB. The receive path LPF cutoff frequency can be set over a 15 MHz to 35 MHz range or simply bypassed. The 10-bit ADC achieves excellent dynamic performance over a 5 MSPS to 80 MSPS span. Both the RxPGA and the ADC offer scalable power consumption allowing power/performance optimization.
The AD9865 provides a highly integrated solution for many broadband modems. It is available in a space saving 64-pin chip scale package and is specified over the commercial (−40°C to +85°C) temperature range.
- Powerline networking
- VDSL and HPNA
Product Lifecycle Production
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
Documentation & Resources
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|Part Number||Material Declaration||Reliability Data||Pin/Package Drawing||CAD Symbols, Footprints & 3D Models|
|AD9865BCPZ||Material Declaration||Reliability Data||64-Lead LFCSP (9mm x 9mm w/ EP)|
|AD9865BCPZRL||Material Declaration||Reliability Data||64-Lead LFCSP (9mm x 9mm w/ EP)|
|Wafer Fabrication Data|
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