LT3073

• Input voltage range: 0.6 V to 5.5 V
• BIAS voltage range: 2.375 V to 5.5 V
• Jumpers program output voltage according to selection matrix: 0.5 V to 4.2 V
• Maximum output current: 3 A
• BNC connectors for noise and PSRR measurement
• Jumper and resistor combinations select either 3.72 A or 1.5 A output current limit and commensurate monitoring or disable programmed current limit and monitoring
• Jumper turns regulator on or off
• Terminals provide output current, temperature, and output regulation status monitoring
• Jumper to margin output voltage ±2.5%
• The VIOC pin of the LT3073 manages power dissipation and PSRR
• Banana jacks minimize V_IN and V_OUT connection voltage drops
• VO+, VO−, and VI+ terminals for regulation and dropout monitoring
• Thermally enhanced, 22-lead, 3 mm × 4 mm x 0.95 mm, LQFN package

The EVAL-LT3073-AZ evaluation board features the LT3073, a 3 A, ultra-low noise, high power-supply rejection ratio (PSRR), 45 mV dropout ultra-fast linear regulator. The input voltage (VIN) range for the VIN power is from 0.6 V to 5.5 V. There are jumpers to set a 3-bit trilevel code that determines the output voltage (VOUT) at preprogrammed levels that range from 0.5 V to 4.2 V. The maximum output current is 3 A. The EVAL-LT3073-AZ requires an external BIAS voltage (VBIAS) that is at least 1.2 V higher than VOUT and is between 2.375 V and 5.5 V.

The LT3073 of the EVAL-LT3073-AZ requires few external components; therefore, simplifying circuit design. External component choice along with careful printed circuit board (PCB) design help optimize noise, PSRR, load transient response, and V_OUT regulation performance. The LT3073 requires capacitors for the internal reference, power input, BIASF pin, and the power output. The internal reference is bypassed with a 16 V, 0805 sized, 4.7 μF capacitor to reduce output noise and program the soft-start. Larger capacitor case sizes and higher voltage ratings decrease 1/f noise for otherwise comparable capacitors. The 22 μF capacitor at the circuit output was chosen for high-frequency PSRR performance and to minimize VOUT deviation during load transients.

The capacitor that bypasses the VIN power for the LT3073 and the corresponding VIN PCB layout can affect PSRR (see the Best PSRR Performance: PCB Layout for Input Traces section for additional information). The EVAL-LT3073-AZ decouples the VIN power with a 47 μF capacitor. Less VIN capacitance can improve PSRR at high frequencies (see the LT3073 data sheet for the minimum capacitor value required for VIN). Note that a bulk 220 μF tantalum polymer capacitor further reduces VIN variation during load transients and reduces input voltage ringing that can be caused by inductive input power leads. The PCB has a footprint for an optional Subminiature Version A (SMA) connector that allows a shielded VIN power connection to the PCB edge, if required.

The EVAL-LT3073-AZ bypasses the BIASF pin with a 2.2 μF capacitor instead of the VBIAS supply input. Because the BIASF pin is isolated from VBIAS by a resistance that is internal to the LT3073, there is less PSRR degradation when BIASF is bypassed compared to when VBIAS is bypassed. Otherwise, the effect on PSRR of the VIN and VBIAS bypass capacitors is similar.

The EVAL-LT3073-AZ has resistors that allow a CURRENT LIMIT jumper to select output current limits of either 1.5 A or 3.72 A.

The CURRENT LIMIT jumper can also disable external current-limit programming by shorting the IMON pin to ground. An IMON terminal is available for current monitoring. The IMON voltage is the product of the resistance that externally programs current limit and the IMON pin current that is 1/3000 of the output current. Externally programmed current limit occurs when the IMON voltage is 1 V.

A POWER jumper (JP1) is available on the EVAL-LT3073-AZ to either connect the EN pin to VBIAS to turn the output on or to ground to disable the output. A TEMP terminal is also available for die temperature monitoring. There is a PG terminal that is pulled up to VBIAS by a 51 kΩ resistor and pulled down by the open-drain, negative channel metal-oxide semiconductor (NMOS) PG pin output for indication of regulator output status and other fault modes. The voltage input-to-output control (VIOC) terminal allows connections for automatically controlling a preregulation voltage. In addition, a MARG jumper can margin the output voltage to either ±2.5%.

Banana jacks minimize voltage drops on VIN and VOUT connections. Bayonet Neill-Concelman (BNC) connectors provide low noise connections to power VIN, VBIAS, and VOUT. The EVAL-LT3073-AZ PCB design uses a split capacitor technique to Kelvin connect the ground terminal of the REF capacitor to the ground terminal of the output capacitor, and the SENSE pin to the positive terminal of the output capacitor. The VO+, VO−, and VI+ terminals Kelvin connect to VIN and VOUT and are the optimum place to observe output voltage regulation and dropout voltage performance. There are test points for BIASF and REF voltages.

The EVAL-LT3073-AZ has placeholders identified on the schematic as optional OPT components that make it convenient to add capacitance (see Figure 8 in the user guide).

For full details on the LT3073, see the LT3073 data sheet, which must be consulted with the user guide when using the EVAL-LT3073- AZ evaluation board. The LT3073 of the EVAL-LT3073-AZ features a thermally enhanced, 22-lead, 3 mm x 4 mm x 0.95 mm LQFN package. Proper board layout is essential for maximum thermal performance.