HMCAD1100

Octal 13/12-Bit 20 to 50 MSPS A/D Converter

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HMCAD1100 Functional Block Diagram slide

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Features

20/40/50 MSPS Maximum Sampling Rate
Ultra Low Power Dissipation
23 mW/Channel at 20MSPS
35 mW/Channel at 40MSPS
41 mW/Channel at 50MSPS
72.2 dB SNR at 8 MHz FIN
0.5 μs Startup from Sleep, 15 μs from Power Down
Reduced Power Dissipation Modes Available
1.7 – 3.6V I/O Supply Voltage
71.5 dB SNR at 8 MHz FIN
34 mW/Channel at 50 MSPS

Internal Reference Circuitry with No External Components Required
Coarse and Fine Gain Control
Internal Offset Correction
1.8V Supply Voltage
Serial LVDS Output
12 and 14-bit Output Available
Package alternatives
9mm x 9mm, 64 pin QFN
14mm x 14mm, 80 pin TQFP

Additional Details

HMCAD1100 is a high performance low power octal analog-to-digital converter (ADC). The ADC is based on a proprietary structure and employs internal reference circuitry, a serial control interface and serial LVDS output data. Data and frame synchronization output clocks are supplied for data capture at the receiver.

Various modes and configuration settings can be applied to the ADC through the serial control interface (SPI). Each channel can be powered down independently and data format can be selected through this interface. A full chip idle mode can be set by a single external pin. Register settings determine the exact function of this external pin.

There are two options for the serial LVDS outputs, 12- bit or 14-bit. In 12-bit mode, the LSB bit from the ADCs are removed in the output stream. In 14-bit mode, a ‘0’ is added in the LSB position. The HMCAD1100 is designed to easily interface with field-programmable gate arrays (FPGAs) from several vendors.

The very low start up times for the HMCAD1100 allows significant power reduction in duty-cycled systems, by utilizing the Sleep Modes or Power Down Mode when the receive path is idle.

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