Overview
Features and Benefits
- Dual-enhanced SHARC+ high performance floating-point cores
- Up to 500 MHz per SHARC+ core
- Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache)
- 32-bit, 40-bit, and 64-bit floating-point support
- 32-bit fixed point
- Byte, short word, word, long word addressed
- arm® Cortex-A5 core
- 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle
- 32 kB L1 instruction cache with parity/32 kB L1 data cache with parity
- 256 kB L2 cache with parity
- Powerful DMA system
- On-chip memory protection
- Integrated safety features
- 17 mm × 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP, RoHS compliant
- Low system power across automotive temperature range
Memory
- Large on-chip L2 SRAM with ECC protection, up to 1 MB
- One L3 interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.5 V capable DDR3L devices), DDR2, or LPDDR1 SDRAM devices
Additional Features
- Security and Protection
- Cryptographic hardware accelerators
- Fast secure boot with IP protection
- Support for arm® TrustZone
- Accelerators
- FIR, IIR offload engines
- Qualified for automotive applications
Product Details
The ADSP-SC57x/ADSP-2157x processors are members of the SHARC® family of products. The ADSP-SC57x processor is based on the SHARC+® dual-core and the arm® Cortex®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.
By integrating a set of industry leading system peripherals and memory, the arm® Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.
Product Categories
Markets and Technologies
ADSP-SC57x and ADSP-2157x Series: Summary and Comparison
Product Lifecycle
Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (2)
Documentation & Resources
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EE-428: Tips and Tricks Using the ADSP-SC57x/ADSP-2157x Processor Boot ROM11/16/2020PDF146 K
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EE-401: ADSP-SC5xx/215xx SHARC+ Processor System Optimization Techniques (Rev. 1)2/9/2018PDF2 M
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EE-399: The Linux Run-Time SHARC Loader on ADSP-SC57x/SC58x Processors (Rev. 3)11/8/2017PDF231 K
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EE-400: Using Cache on ADSP-SC5xx/ADSP-215xx SHARC+ Processors (Rev. 1)9/25/2017PDF405K
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EE-397: Estimating Power for ADSP-SC57x/ADSP-2157x SHARC+® Processors (Rev. 1 - July 20, 2017)7/21/2017PDF453 K
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EE-387: Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/ADSP-215xx Processors (Rev. 3)1/8/2016PDF2 M
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EE-253: Power Bypass Decoupling of SHARC® Processors (Rev. 1)12/5/2006PDF354 kB
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EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev. 1)2/15/2005PDF90 kB
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SHARC+ Core Programming Reference5/1/2021PDF4 M
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ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference (Rev. 1.1)6/14/2016PDF15 M
Software & Systems Requirements
Middleware
Operating Systems and Middleware
Middleware
Lightweight TCP/IP (lwIP) Stack
Software Development Tools
CrossCore® Embedded Studio
CCES is a world-class integrated development environment (IDE) for the ADI Blackfin®, SHARC® and Arm® processor families.
SigmaStudio®
CrossCore® Utilities
CrossCore Utilities provides several utilities for use with Cortex-M processors. These utilities have previously been distributed within various Board Support Packages for the IAR and Keil toolchains, and are collected together in this product for convenient maintenance.
Tools & Simulations
IBIS Models
Design Resources
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
PCN-PDN Information
Support & Discussions
Sample & Buy
Ordering FAQs
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Sampling
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Evaluation Boards
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.