AD5110 - FAQ
What is the resistance tolerance of the digital potentiometers?
It is either a maximum of ±30% or ±20%. Please see datasheets.
If using the pot in the 3-terminal voltage divider mode (without any series resistor), the tolerance is irrelevant because the resistances RWA and RWB are ratiometric. If using the pot in the 2 terminal rheostat mode, you should account for the worst case variation. On the AD525X family and AD5235 digipots resistance tolerance is stored in the EEPROM at factory with an accuracy of 0.1%. Thus users can retrieve the resistance tolerance and calibrate the system accordingly.
What is the maximum current I can force into the digital potentiometer?
The maximum current is limited by 3 boundaries at a given resistance setting. They are the terminal voltage range limit, the power dissipation, and the maximum current handling capabilities of the internal switches. Voltage limitation is the dominant factor in most settings. 1 kΩ and 10 kΩ settings yield 5.5mA and 0.55mA maximum respectively for 5V digipots. Maximum power dissipation becomes a factor at low resistance values. At zero scale with a minimum wiper resistance, 20mA is the max allowable pulse current limit imposed by the switches. There are Imax vs. Code graphs shown in the new product datasheets.
Is there a particularly low-power digital potentiometer?
Yes. The AD5165 offers ultra-low power consumption.
Is there a power up sequence I should follow?
Yes, it is good practice to power VDD first and VSS second. The order of VA, VB, and VW is not important but they should be powered last. There are ESD protection diodes between the VDD and the A, B, and W terminals. For example, the cathode of one of the diodes connects to VDD and the anode connects to the A terminal. As a result, any voltage occurring at the A terminal before VDD will forward bias the diode and power the VDD. For AD5231/AD5232/AD5233/AD5235 only, the digital signals should also be powered after VDD. Please refer to datasheets for additional information regarding digital signal sequence.
Is there a dependency between the logic level and power consumption?
Yes. If the logical level is lower than the supply VDD, the CMOS gates will not switch completely and the part will consume more power.
Regarding the spec on R-DNL, I am only concerned with relative adjustments. I'm not concerned with the actual value of the resistor in the digipot but need the digipot to be monotonic.
Yes, the digipot is monotonic.
If I use the digital potentiometer in a "dry" circuit (current through wiper < 1 pA), will it behave as a linear resistor in rheostat mode?
It is linear. RWB is made up by RS + RSW where RS and RSW are step resistors and a switch resistor respectively.
Is digital potentiometer a real replacement for mechanical potentiometer or are there restrictions regarding voltage potentials?
Strictly speaking, digital potentiometer is not an exact replacement for mechanical potentiometer. The larger one of VA and VB must be smaller than or equal to VDD, and the smaller one of VA and VB must be greater than or equal to VSS, or GND if the part does not have a VSS pin. For example, if the desired VA and VB are +2V and -2V, then VDD must be >= +2V and VSS must be <= -2V. In any case, voltages across terminals W-A, W-B, or A-B of all digital potentiometers (except AD7376, AD5260/2, AD5280/82, AD5290, and AD5263) should be limited to |5V|, the polarity constraint.
I would like to know how the digital potentiometer is built. How ideal are the wiper switches?
It is a purely CMOS device. All switches are large CMOS transmission gates operated in the linear region to yield low uniform RDS(on). All resistor elements are poly silicon or thin film resistors.
How is the resistance matching device to device?
Assuming the parts come from the same batch, the resistance matching device-to-device is believed to be ±1% as well.
How many write cycles can the EEMEM go through before it fails?
How good is the resistance matching between Ch1 and Ch2 in the dual digital potentiometer?
The matching is typically 0.1-0.2% and we usually specify ±1% as a maximum.
Will the data in the EEMEM need to be refreshed after 15 yrs when it is operated at 55°C?
Yes. The EEPROM cells will lose charge over the 15 years when operating at 55°C. For other operating temperatures please see the "Retention vs. TJ Junction Temperature" plot in the AD5232 datasheet. Such data applies to all nonvolatile memory digital potentiometers.
What is the tempco of the digital potentiometer?
There are two components that make up the resistance at any given setting. They are the poly silicon resistors (step resistor Rs) and the CMOS switch resistor (Rsw=50 Ω at 5V supply). Together they add up such that RWB = RS + RW, RS = RAB / 2N * D, where D is the decimal code. The tempco of the step resistor, which is published in the datasheet, is typically in the range of a few tens of ppm/°C for thin film or a few hundred ppm/°C for poly. The resistance of the switch, on the other hand, doubles in 100°C. As a result, the overall tempco is nonlinear and it is worse off at low value codes where the switch resistance dominates. Users should refer to the tempco graphs in the datasheets for more detailed information
Why are some digital potentiometers' maximum operating temperature only 85°C instead of the standard 125°C?
The digipots that contain EEPROMs usually only work up to 85°C, and this is because EEPROMs are only guaranteed to safely operate below 85°C.
Can a digipot be used to construct a programmable high current source?
A current boosted or Howland current pump can be used as suggested by the AD5231 datasheet.
Are all digital potentiometers limited to |5V|?
No. The AD7376 and AD5290 handle ±15V or single +30V. The AD5260/5262/5280/5282/5263 all handle ±5V or single +12V. The remaining ones are limited to |5V|.
After the specified EEMEM data retention timeout period, can the power be turned off and back on so that the part is considered "refreshed"?
No. That will only refresh the RDAC register but not the EEPROM. The data will have to be reloaded again after 15 years in order to put a fresh charge into the EEPROM cell. This can be done by writing the RDAC wiper register data back to the EEPROM before the end of 15 years.
Can I cascade, serialize, or parallel multiple digital potentiometers to get the resistance or resolution I need? My requirement is for a 250 Ω digital potentiometer with approximately 1 Ω/step. I plan to use four 1 kΩ AD8403 in parallel with each set to nominally the same value.
Yes, see the application note AN-582 "Resolution Enhancements of Digital Potentiometers with Multiple Devices."
Are ADI's digital potentiometers suitable for use in photodetector amplifiers and will they suffer from leakage currents which could affect the gain of the circuit?
We manufacture this product with a very low leakage analog switch process, which results in low leakage currents. We usually spec a common mode leakage current of 1nA typical.
Can a digitally controlled variable resistor withstand greater than 20mA?
Do digital potentiometers handle bipolar and AC operations?
Yes, we have digital potentiometers with dual ±2.5V, ±5V, or ±15V supplies that can handle bipolar or AC operation. You can still achieve AC operation with a single DC supply if you raise the DC offset. Terminals A, B, and W have no polarity constraints with respect to each other.
Does the memory allow the device to return to the last stored value without an update from a micro?
Yes. It is automatically set to the previously stored value every time the device is powered-on.
For dual supply digital potentiometers, if VDD/VSS are +2.5V/-2.5V respectively, can digital inputs be fed from a standard 3.3V CMOS logic component without logic level translation? What are the logic level thresholds when VDD is +2.5V and VSS is -2.5V?
For most of our digipots, you may use a standard 3.3V on the digital inputs. For AD5231/2/3/5, however, the digital input levels cannot be higher than 0.3V above VDD or 0.3V below ground, or +2.8V and -0.3V in this case. Otherwise, the internal protection diodes may be damaged. The logical level thresholds differ from parts to parts and are also supply dependent. For example, for AD5231/2/3/5, at VDD= +2.5V and VSS = -2.5V the logical level high and low are +2.0V and +0.5V, respectively. Please check datasheets for more details.
For digital potentiometers that do not have nonvolatile memory, what is the state during power up?
Most of our digital potentiometers contain P.O.R. (power on preset) circuitry which presets the wiper-to-terminal resistance to the middle value of the terminal-to-terminal resistance. For example, If RAB = 10 kΩ, then at power-up RWB = RWA = 5 kΩ. For the digital potentiometers that do not have this feature, the wiper-to-terminal resistance can be anything at power-up. Please check the datasheets for more details.